公开(公告)号：US20240213198A1

公开(公告)日：2024-06-27

申请号：US18087517

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Liang He ,  Yue Deng ,  Gang Duan ,  Jung Kyu Han ,  Ali Lehaf ,  Srinivas Pietambaram

IPC: H01L23/00 ,  H01L23/538

CPC classification number: H01L24/13 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/13541 ,  H01L2224/1358 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13684 ,  H01L2224/16013 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841

Abstract: An electronic package comprises a first die having at least one first interconnect with solder over or under a first metal feature. A second die has at least one second interconnect to the first die, each second interconnect comprising a second metal feature comprising copper, solder over or under the second metal feature, and a layer between the solder and the second metal feature, wherein the layer comprises iron and has a different material than material of the first interconnect.

公开(公告)号：US20230197543A1

公开(公告)日：2023-06-22

申请号：US17557142

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Liang He ,  Yue Deng ,  Jung Kyu Han ,  Gang Duan

IPC: H01L23/29 ,  H01L23/18

CPC classification number: H01L23/291 ,  H01L23/18 ,  H01L23/298

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface with conductive contacts, in a first layer; a first material surrounding the first die and extending along a thickness of the first die from the second surface, and wherein the first material includes first particles having an average diameter between 200 and 500 nanometers; a second material surrounding the first die and extending along the thickness of the first die from the first surface, and wherein the second material includes second particles having an average diameter between 0.5 and 12 microns; an interface portion, between the first and second materials, including the first and second particles; and a second die, in a second layer on the first layer, electrically coupled to the conductive contacts on the first die.

公开(公告)号：US20240332134A1

公开(公告)日：2024-10-03

申请号：US18193182

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Liang He ,  Jung Kyu Han ,  Gang Duan

IPC: H01L23/495 ,  H01L21/768 ,  H01L23/00 ,  H01L23/15 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/49513 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/5283 ,  H01L23/53228 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/05147 ,  H01L2224/06131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131

Abstract: Methods and apparatus to mitigate electromigration are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, a contact pad at least partially extending though or positioned on the dielectric substrate, the contact pad including copper, and a metal interconnect coupled to the contact pad, the interconnect including indium.