公开(公告)号：US09645930B2

公开(公告)日：2017-05-09

申请号：US13922072

申请日：2013-06-19

Applicant: INTEL Corporation

Inventor： Christopher J. Hughes ,  Daehyun Kim ,  Jong Soo Park ,  Richard M. Yoo

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0813 ,  G06F12/0817

CPC classification number: G06F12/0831 ,  G06F12/0813 ,  G06F12/0817 ,  G06F2212/621 ,  Y02D10/13

Abstract: Technologies for dynamic home tile mapping are described. an address request can be received from a processing core, the processing core being associated with a home tile table, the home tile table including respective mappings of one or more directory addresses to one or more home tiles. A buffer can be scanned to identify a presence of the address within the buffer. Based on an identification of the presence of the address within the buffer, a home tile identifier corresponding to the address can be provided from the buffer.

公开(公告)号：US20160139897A1

公开(公告)日：2016-05-19

申请号：US15005781

申请日：2016-01-25

Applicant: Intel Corporation

Inventor： Nalini Vasudevan ,  Jayashankar Bharadwaj ,  Christopher J. Hughes ,  Milind B. Girkar ,  Mark J. Charney ,  Robert Valentine ,  Victor W. Lee ,  Daehyun Kim ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F9/45

CPC classification number: G06F8/443 ,  G06F8/433 ,  G06F8/452 ,  G06F8/70 ,  G06F9/30036 ,  G06F9/38 ,  G06F9/3836

Abstract: Loop vectorization methods and apparatus are disclosed. An example method includes prior to executing an original loop having iterations, analyzing, via a processor, the iterations of the original loop, identifying a dependency between a first one of the iterations of the original loop and a second one of the iterations of the original loop, after identifying the dependency, vectorizing a first group of the iterations of the original loop based on the identified dependency to form a vectorization loop, and setting a dynamic adjustment value of the vectorization loop based on the identified dependency.

Abstract translation: 公开了环向量化方法和装置。 示例性方法包括在执行具有迭代的原始循环之前，经由处理器分析原始循环的迭代，识别原始循环的第一迭代和原始循环的第二迭代之间的依赖关系 循环，在识别依赖性之后，基于所识别的依赖关系对原始循环的第一组迭代进行矢量化以形成矢量化循环，以及基于所识别的依赖关系来设置矢量化循环的动态调整值。

公开(公告)号：US08954674B2

公开(公告)日：2015-02-10

申请号：US14048291

申请日：2013-10-08

Applicant: Intel Corporation

Inventor： Daehyun Kim ,  Christopher J. Hughes ,  Yen-Kuang Chen ,  Partha Kundu

IPC: G06F12/00 ,  G11C7/10 ,  G06F12/08

CPC classification number: G06F12/0806 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/6026 ,  G06F2212/62 ,  G11C7/1072 ,  G11C7/1075 ,  Y02D10/13

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract translation: 分散/收集技术优化非结构化流式存储器访问，通过仅访问精细粒度的有用数据来提供片外带宽效率，并通过支持地址计算，数据混洗和格式转换来卸载内存访问开销。

公开(公告)号：US20190236013A1

公开(公告)日：2019-08-01

申请号：US16382833

申请日：2019-04-12

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Daehyun Kim ,  Jong Soo Park ,  Richard M. Yoo

IPC: G06F12/0831 ,  G06F12/0817 ,  G06F12/0813

CPC classification number: G06F12/0831 ,  G06F12/0813 ,  G06F12/0817 ,  G06F2212/621 ,  Y02D10/13

Abstract: Technologies for migration of dynamic home tile mapping are described. An apparatus includes means for receiving coherence messages from other processor cores on the die, means for recording locations from which the coherence messages originate and means for determining distances between the requested home tiles and the locations from which the coherence messages originate. The apparatus includes means for determining whether an average distance between a particular home tile, whose identifier is stored in the home tile table, exceeds a threshold. When the average distance exceeds the defined threshold, the apparatus includes means for migrating the particular home tile to another location.

公开(公告)号：US10152325B2

公开(公告)日：2018-12-11

申请号：US15426963

申请日：2017-02-07

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Jong Soo Park

IPC: G06F9/00 ,  G06F9/30 ,  G06F9/44 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0875 ,  G06F9/54

Abstract: Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core.

公开(公告)号：US09678750B2

公开(公告)日：2017-06-13

申请号：US13795234

申请日：2013-03-12

Applicant: Intel Corporation

Inventor： Mikhail Smelyanskiy ,  Victor Lee ,  Christopher Hughes ,  Daehyun Kim ,  Yen-Kuang Chen ,  Changkyu Kim ,  Jatin Chhugani ,  Anthony D. Nguyen ,  Sanjeev Kumar

IPC: G06F15/00 ,  G06F15/76 ,  G06F9/30 ,  G06F9/38 ,  G06T5/40 ,  H04N1/407 ,  G06K9/62

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3885 ,  G06K9/6212 ,  G06T5/40 ,  H04N1/4074

Abstract: In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.

公开(公告)号：US09372678B2

公开(公告)日：2016-06-21

申请号：US14129438

申请日：2013-06-14

Applicant: Intel Corporation

Inventor： Ganesh Bikshandi ,  Daehyun Kim

IPC: G06F9/45

CPC classification number: G06F8/443 ,  G06F7/4806 ,  G06F7/556 ,  G06F8/4434 ,  G06F8/452 ,  G06F17/10 ,  G06F2207/5561

Abstract: Technologies for optimizing complex exponential calculations include a computing device with optimizing compiler. The compiler parses source code, optimizes the parsed representation of the source code, and generates output code. During optimization, the compiler identifies a loop in the source code including a call to the exponential function having an argument that is a loop-invariant complex number multiplied by the loop index variable. The compiler tiles the loop to generate a pair of nested loops. The compiler generates code to pre-compute the exponential function and store the resulting values in a pair of coefficient arrays. The size of each coefficient array may be equal to the square root of the number of loop iterations. The compiler applies rewrite rules to replace the exponential function call with a multiplicative expression of one element from each of the coefficient arrays. Other embodiments are described and claimed.

Abstract translation: 用于优化复数指数计算的技术包括具有优化编译器的计算设备。 编译器解析源代码，优化源代码的解析表示，并生成输出代码。 在优化期间，编译器识别源代码中的循环，包括对具有循环不变复数乘以循环索引变量的参数的指数函数的调用。 编译器平铺循环以生成一对嵌套循环。 编译器生成代码以预先计算指数函数，并将结果值存储在一对系数数组中。 每个系数数组的大小可以等于循环次数的平方根。 编译器使用重写规则来替换来自每个系数数组的一个元素的乘法表达式的指数函数调用。 描述和要求保护其他实施例。

公开(公告)号：US09323672B2

公开(公告)日：2016-04-26

申请号：US14585573

申请日：2014-12-30

Applicant: Intel Corporation

Inventor： Daehyun Kim ,  Christopher J. Hughes ,  Yen-Kuang Chen ,  Partha Kundu

IPC: G06F12/08 ,  G11C7/10

CPC classification number: G06F12/0806 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/6026 ,  G06F2212/62 ,  G11C7/1072 ,  G11C7/1075 ,  Y02D10/13

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

公开(公告)号：US09244677B2

公开(公告)日：2016-01-26

申请号：US13630147

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Nalini Vasudevan ,  Jayashankar Bharadwaj ,  Christopher J. Hughes ,  Milind B. Girkar ,  Mark J Charney ,  Robert Valentine ,  Victor W. Lee ,  Daehyun Kim ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F9/44 ,  G06F9/38 ,  G06F9/45

CPC classification number: G06F8/443 ,  G06F8/433 ,  G06F8/452 ,  G06F8/70 ,  G06F9/30036 ,  G06F9/38 ,  G06F9/3836

Abstract: Loop vectorization methods and apparatus are disclosed. An example method includes setting a dynamic adjustment value of a vectorization loop; executing the vectorization loop to vectorize a loop by grouping iterations of the loop into one or more vectors; identifying a dependency between iterations of the loop as; and setting the dynamic adjustment value based on the identified dependency.

Abstract translation: 公开了环向量化方法和装置。 示例性方法包括设置矢量化循环的动态调整值; 执行向量化循环以通过将循环的迭代分组为一个或多个向量来矢量化循环; 识别循环迭代之间的依赖关系; 并且基于所识别的依赖关系来设置动态调整值。

公开(公告)号：US09158702B2

公开(公告)日：2015-10-13

申请号：US13730507

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Daya Shankar Khudia ,  Daehyun Kim ,  Jong Soo Park ,  Richard M. Yoo

IPC: G06F12/12 ,  G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/123 ,  G06F12/127

Abstract: An apparatus and method for implementing a scratchpad memory within a cache using priority hints. For example, a method according to one embodiment comprises: providing a priority hint for a scratchpad memory implemented using a portion of a cache; determining a page replacement priority based on the priority hint; storing the page replacement priority in a page table entry (PTE) associated with the page; and using the page replacement priority to determine whether to evict one or more cache lines associated with the scratchpad memory from the cache.

Abstract translation: 一种使用优先提示在高速缓存中实现暂存器存储器的装置和方法。 例如，根据一个实施例的方法包括：为使用高速缓存的一部分实现的暂存器存储器提供优先提示; 基于优先提示确定页面替换优先级; 将所述页面替换优先级存储在与所述页面相关联的页面表项（PTE）中; 以及使用页面替换优先级来确定是否从高速缓存驱逐与暂存器存储器相关联的一个或多个高速缓存行。