公开(公告)号：US09645930B2

公开(公告)日：2017-05-09

申请号：US13922072

申请日：2013-06-19

Applicant: INTEL Corporation

Inventor： Christopher J. Hughes ,  Daehyun Kim ,  Jong Soo Park ,  Richard M. Yoo

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0813 ,  G06F12/0817

CPC classification number: G06F12/0831 ,  G06F12/0813 ,  G06F12/0817 ,  G06F2212/621 ,  Y02D10/13

Abstract: Technologies for dynamic home tile mapping are described. an address request can be received from a processing core, the processing core being associated with a home tile table, the home tile table including respective mappings of one or more directory addresses to one or more home tiles. A buffer can be scanned to identify a presence of the address within the buffer. Based on an identification of the presence of the address within the buffer, a home tile identifier corresponding to the address can be provided from the buffer.

公开(公告)号：US09250914B2

公开(公告)日：2016-02-02

申请号：US14137218

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Daehyun Kim ,  Camilo A. Moreno ,  Jong Soo Park ,  Richard M. Yoo

IPC: G06F12/00 ,  G06F9/38 ,  G06F15/80 ,  G06F12/08 ,  G06F11/07

CPC classification number: G06F9/3806 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/382 ,  G06F9/3834 ,  G06F9/3836 ,  G06F11/0724 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0897 ,  G06F15/80

Abstract: An apparatus and method for determining whether to execute an atomic operation locally or remotely. For example, one embodiment of a processor comprises: a decoder to decode an atomic operation on a local core; prediction logic on the local core to estimate a cost associated with execution of the atomic operation on the local core and a cost associated with execution of the atomic operation on a remote core; and the remote core to execute the atomic operation remotely if the prediction logic determines that the cost for execution on the local core is relatively greater than the cost for execution on the remote core; and the local core to execute the atomic operation locally if the prediction logic determines that the cost for local execution on the local core is relatively less than the cost for execution on the remote core.

Abstract translation: 一种用于确定是在本地还是远程执行原子操作的装置和方法。 例如，处理器的一个实施例包括：解码器，用于解码局部核心上的原子操作; 本地核心上的预测逻辑来估计与本地核心上的原子操作的执行相关的成本以及与在远程核心上执行原子操作相关联的成本; 以及所述远程核心，如果所述预测逻辑确定所述本地核上的执行成本相对大于所述远程核上的执行成本，则远程执行所述原子操作; 如果预测逻辑确定本地核心上的本地执行成本相对低于在远程核心上执行的成本，本地核心将在本地执行原子操作。

公开(公告)号：US20190236013A1

公开(公告)日：2019-08-01

申请号：US16382833

申请日：2019-04-12

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Daehyun Kim ,  Jong Soo Park ,  Richard M. Yoo

IPC: G06F12/0831 ,  G06F12/0817 ,  G06F12/0813

CPC classification number: G06F12/0831 ,  G06F12/0813 ,  G06F12/0817 ,  G06F2212/621 ,  Y02D10/13

Abstract: Technologies for migration of dynamic home tile mapping are described. An apparatus includes means for receiving coherence messages from other processor cores on the die, means for recording locations from which the coherence messages originate and means for determining distances between the requested home tiles and the locations from which the coherence messages originate. The apparatus includes means for determining whether an average distance between a particular home tile, whose identifier is stored in the home tile table, exceeds a threshold. When the average distance exceeds the defined threshold, the apparatus includes means for migrating the particular home tile to another location.

公开(公告)号：US09158702B2

公开(公告)日：2015-10-13

申请号：US13730507

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Daya Shankar Khudia ,  Daehyun Kim ,  Jong Soo Park ,  Richard M. Yoo

IPC: G06F12/12 ,  G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/123 ,  G06F12/127

Abstract: An apparatus and method for implementing a scratchpad memory within a cache using priority hints. For example, a method according to one embodiment comprises: providing a priority hint for a scratchpad memory implemented using a portion of a cache; determining a page replacement priority based on the priority hint; storing the page replacement priority in a page table entry (PTE) associated with the page; and using the page replacement priority to determine whether to evict one or more cache lines associated with the scratchpad memory from the cache.

Abstract translation: 一种使用优先提示在高速缓存中实现暂存器存储器的装置和方法。 例如，根据一个实施例的方法包括：为使用高速缓存的一部分实现的暂存器存储器提供优先提示; 基于优先提示确定页面替换优先级; 将所述页面替换优先级存储在与所述页面相关联的页面表项（PTE）中; 以及使用页面替换优先级来确定是否从高速缓存驱逐与暂存器存储器相关联的一个或多个高速缓存行。

公开(公告)号：US10678689B2

公开(公告)日：2020-06-09

申请号：US16382833

申请日：2019-04-12

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Daehyun Kim ,  Jong Soo Park ,  Richard M. Yoo

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0813 ,  G06F12/0817

Abstract: Technologies for migration of dynamic home tile mapping are described. An apparatus includes means for receiving coherence messages from other processor cores on the die, means for recording locations from which the coherence messages originate and means for determining distances between the requested home tiles and the locations from which the coherence messages originate. The apparatus includes means for determining whether an average distance between a particular home tile, whose identifier is stored in the home tile table, exceeds a threshold. When the average distance exceeds the defined threshold, the apparatus includes means for migrating the particular home tile to another location.

公开(公告)号：US09323525B2

公开(公告)日：2016-04-26

申请号：US14190404

申请日：2014-02-26

Applicant: Intel Corporation

Inventor： Daehyun Kim ,  Jong Soo Park ,  Dong Hyuk Woo ,  Richard M. Yoo ,  Christopher J. Hughes

IPC: G06F9/30 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F9/30036 ,  G06F9/30189 ,  G06F9/3887 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/348 ,  G06F2201/81 ,  G06F2201/88 ,  Y02D10/34

Abstract: In an embodiment, a processor includes a vector execution unit having a plurality of lanes to execute operations on vector operands, a performance monitor coupled to the vector execution unit to maintain information regarding an activity level of the lanes, and a control logic coupled to the performance monitor to control power consumption of the vector execution unit based at least in part on the activity level of at least some of the lanes. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括具有多个通道以执行向量操作数的操作的向量执行单元，耦合到向量执行单元的性能监视器，以维护关于通道的活动级别的信息，以及耦合到该通道的控制逻辑 性能监视器，用于至少部分地基于至少一些通道的活动水平来控制向量执行单元的功率消耗。 描述和要求保护其他实施例。

公开(公告)号：US10303606B2

公开(公告)日：2019-05-28

申请号：US15465097

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Daehyun Kim ,  Jong Soo Park ,  Richard M. Yoo

IPC: G06F12/0813 ,  G06F12/0817 ,  G06F12/0831

Abstract: Technologies for migration of dynamic home tile mapping are described. A cache controller can receive coherence messages from other processor cores on the die. The cache controller records locations from which the coherence messages originate and determine distances between the requested home tiles and the locations from which the coherence messages originate. The cache controller determines whether an average distance between a particular home tile, whose identifier is stored in the home tile table, exceeds a threshold. When the average distance exceeds the defined threshold, the cache controller migrates the particular home tile to another location.

公开(公告)号：US20170192891A1

公开(公告)日：2017-07-06

申请号：US15465097

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Daehyun Kim ,  Jong Soo Park ,  Richard M. Yoo

IPC: G06F12/0817 ,  G06F12/0813 ,  G06F12/0831

CPC classification number: G06F12/0831 ,  G06F12/0813 ,  G06F12/0817 ,  G06F2212/621 ,  Y02D10/13

Abstract: Technologies for migration of dynamic home tile mapping are described. A cache controller can receive coherence messages from other processor cores on the die. The cache controller records locations from which the coherence messages originate and determine distances between the requested home tiles and the locations from which the coherence messages originate. The cache controller determines whether an average distance between a particular home tile, whose identifier is stored in the home tile table, exceeds a threshold. When the average distance exceeds the defined threshold, the cache controller migrates the particular home tile to another location.