公开(公告)号：US20210066178A1

公开(公告)日：2021-03-04

申请号：US17098000

申请日：2020-11-13

Applicant: Intel Corporation

Inventor： MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Dinesh Somasekhar

IPC: H01L23/498 ,  H01L23/00 ,  H05K1/18 ,  H01L27/02 ,  H03K19/1776 ,  H01L25/065

Abstract: An integrated circuit package may include a semiconductor die on a first side of the integrated circuit package, a first ball grid array (BGA) connection on the first side of the integrated circuit package, and a second BGA connection on a second side of the integrated circuit package. The integrated circuit package may include one or more traces that route data from the first BGA connection and the second BGA connection.

公开(公告)号：US12153866B2

公开(公告)日：2024-11-26

申请号：US18327045

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Sean R. Atsatt ,  Lai Guan Tang

IPC: G06F30/34 ,  G06F15/78 ,  H03K19/17736 ,  H03K19/17796 ,  H04L12/43

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

公开(公告)号：US20240028544A1

公开(公告)日：2024-01-25

申请号：US18478003

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Dheeraj Subbareddy ,  Kavitha Prasad ,  Ankireddy Nalamalpu ,  Harsha Gupta

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/4282

Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.

公开(公告)号：US20230352431A1

公开(公告)日：2023-11-02

申请号：US18300329

申请日：2023-04-13

Applicant: Intel Corporation

Inventor： MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

IPC: H01L23/00 ,  G06F13/38 ,  H01L25/065 ,  G06F13/42 ,  G06F13/14

CPC classification number: H01L24/18 ,  G06F13/385 ,  H01L25/0655 ,  G06F13/4265 ,  G06F13/14 ,  G06F13/4221 ,  H01L25/0652

Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

公开(公告)号：US11789883B2

公开(公告)日：2023-10-17

申请号：US16103709

申请日：2018-08-14

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Dheeraj Subbareddy ,  Kavitha Prasad ,  Ankireddy Nalamalpu ,  Harsha Gupta

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/4282

Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.

公开(公告)号：US20230306173A1

公开(公告)日：2023-09-28

申请号：US18327045

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Sean R. Atsatt ,  Lai Guan Tang

IPC: G06F30/34 ,  H03K19/17736 ,  H04L12/43 ,  G06F15/78 ,  H03K19/17796

CPC classification number: G06F30/34 ,  H03K19/17744 ,  H04L12/43 ,  G06F15/7825 ,  H03K19/17796

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

公开(公告)号：US11700002B2

公开(公告)日：2023-07-11

申请号：US17556917

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Harsha Gupta ,  James Ball ,  Kavitha Prasad ,  Sean R. Atsatt

IPC: H04L12/28 ,  H03K19/17736 ,  H03K19/17796 ,  H04L41/5019 ,  H04L41/5003

CPC classification number: H03K19/17736 ,  H03K19/17796 ,  H04L41/5019 ,  H04L41/5003

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

公开(公告)号：US11669472B2

公开(公告)日：2023-06-06

申请号：US17543433

申请日：2021-12-06

Applicant: Intel Corporation

Inventor： Lai Guan Tang ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Chee Hak Teh ,  Md Altaf Hossain

IPC: G06F13/20 ,  G06F13/40

CPC classification number: G06F13/20 ,  G06F13/4027

Abstract: Systems and method include one or more die coupled to an interposer. The interposer includes interconnection circuitry configured to electrically connect the one or more die together via the interposer. The interposer also includes translation circuitry configured to translate communications as they pass through the interposer. For instance, in the interposer, the translation circuitry translates communications, in the interposer, from a first protocol of a first die of the one or more die to a second protocol of a second die of the one or more die.

公开(公告)号：US11621713B2

公开(公告)日：2023-04-04

申请号：US17408129

申请日：2021-08-20

Applicant: Intel Corporation

Inventor： Lai Guan Tang ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

IPC: H03K19/177 ,  H01L25/065 ,  H03K19/17704 ,  H03K19/17724 ,  H03K19/1776 ,  H03K19/17736 ,  G06F30/30 ,  G06F30/32 ,  G06F30/34

Abstract: Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.

公开(公告)号：US11595045B2

公开(公告)日：2023-02-28

申请号：US17359466

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Robert Sankman ,  Ravindranath Mahajan ,  Gregg William Baeckler

IPC: H03K19/1776 ,  H01L25/18 ,  H01L23/367

Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.