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公开(公告)号：US10957095B2
公开(公告)日：2021-03-23
申请号：US16056222
申请日：2018-08-06
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Won-Jong Lee , Gabor Liktor , John G. Gierach , Pawel Majewski , Prasoonkumar Surti , Carsten Benthin , Sven Woop , Thomas Raoux
Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
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公开(公告)号：US20200334200A1
公开(公告)日：2020-10-22
申请号：US16869223
申请日：2020-05-07
Applicant: Intel Corporation
Inventor： Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20200160534A1
公开(公告)日：2020-05-21
申请号：US16688403
申请日：2019-11-19
Applicant: Intel Corporation
Inventor： Hugues Labbe , Tomer Bar-On , John G. Gierach , Gabor Liktor , Andrew T. Lauritzen
IPC: G06T7/194 , H04N19/597 , G06T7/11 , G06T7/00 , G06T15/20 , H04N21/00 , G06T15/50 , H04N21/4402 , H04N21/2343 , H04N19/436 , H04N19/167 , H04N21/478 , H04N19/132 , H04N21/81 , H04N19/587 , H04N19/46
Abstract: Systems, apparatuses and methods may provide for technology that partitions a three-dimensional (3D) scene into a plurality of layers including at least a foreground layer and a background layer. Additionally, the foreground layer may be rendered at a first rate and the background layer may be rendered at a second frame rate, wherein the first frame rate is greater than the second frame rate. In one example, the foreground layer and the background layer are composited into a frame.
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24.发明申请公开(公告)号：US20180300930A1
公开(公告)日：2018-10-18
申请号：US15488824
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Jonathan Kennedy , Gabor Liktor , Jeffery S. Boles , Slawomir Grajewski , Balaji Vembu , Travis T. Schluessler , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Altug Koker , Jacek Kwiatkowski
CPC classification number: G06T15/005 , A63F13/53 , A63F2300/303 , A63F2300/66
Abstract: Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices.
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25.发明申请公开(公告)号：US20180300841A1
公开(公告)日：2018-10-18
申请号：US15488842
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Travis T. Schluessler , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Altug Koker , Jacek Kwiatkowski , Ingo Wald , Jefferson Amstutz , Johannes Guenther , Gabor Liktor , Elmoustapha Ould-Ahmed-Vall
Abstract: Systems, apparatuses, and methods may provide for technology to process graphical data, and to modify a runtime environment in a parallel computing platform for a graphic environment.
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Patent Agency Ranking
26.发明申请公开(公告)号：US20180300145A1
公开(公告)日：2018-10-18
申请号：US15488988
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Andrew T. Lauritzen , Gabor Liktor , Tomer Bar-On , Hugues Labbe , John G. Gierach , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Abhishek R. Appu , Balaji Vembu , Altug Koker
IPC: G06F9/38 , G06F9/30 , G06F12/0875 , G06F12/0862
CPC classification number: G06F12/0862 , G06F9/30145 , G06F9/3802 , G06F9/3851 , G06F9/3887 , G06F12/0811 , G06F12/0855 , G06F12/0875 , G06F2212/1016 , G06F2212/452 , G06F2212/455 , G06F2212/602 , G06F2212/6024 , G06T1/20
Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.
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公开(公告)号：US20170287100A1
公开(公告)日：2017-10-05
申请号：US15157667
申请日：2016-05-18
Applicant: Intel Corporation
Inventor： Gabor Liktor , Karthik Vaidyanathan
CPC classification number: G06T1/20 , G06F12/0871 , G06F2212/1016 , G06F2212/302 , G06F2212/401 , G06T15/06 , G06T17/005
Abstract: Incremental encoding of Bounding Volume Hierarchies (BVH) enables coarse quantization of bounding volumes, significantly reducing their memory footprint. However, reducing the size of the BVH alone does not yield a comparable reduction in memory bandwidth in some embodiments. While the bounding volumes of the BVH nodes can be aggressively quantized, the size of the child node pointers remains a significant overhead. A two-level clustering method introduces a memory layout and node addressing scheme, which allows the reordering of BVH nodes to reduce their memory footprint in hardware ray tracing systems using reduced precision ray traversal.
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公开(公告)号：US11710267B2
公开(公告)日：2023-07-25
申请号：US17478161
申请日：2021-09-17
Applicant: Intel Corporation
Inventor： Jonathan Kennedy , Gabor Liktor , Jeffery S. Boles , Slawomir Grajewski , Balaji Vembu , Travis T. Schluessler , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Altug Koker , Jacek Kwiatkowski
IPC: G06T15/00 , A63F13/355
CPC classification number: G06T15/005 , A63F13/355 , A63F2300/66
Abstract: Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices.
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公开(公告)号：US20230148225A1
公开(公告)日：2023-05-11
申请号：US17958211
申请日：2022-09-30
Applicant: Intel Corporation
Inventor： Manu Mathew Thomas , Karthik Vaidyanathan , Anton Kaplanyan , SungYe Kim , Gabor Liktor
CPC classification number: G06T5/002 , G06K9/6232 , G06T15/06 , G06T3/4046 , G06T3/4053 , G06T1/20 , G06T5/20 , G06T3/0093 , G06T2210/36
Abstract: Joint denoising and supersampling of graphics data is described. An example of a graphics processor includes multiple processing resources, including a least a first processing resource including a pipeline to perform a supersampling operation; and the pipeline including circuitry to jointly perform denoising and supersampling of received ray tracing input data, the circuitry including first circuitry to receive input data associated with an input block for a neural network, second circuitry to perform operations associated with a feature extraction and kernel prediction network of the neural network, and third circuitry to perform operations associated with a filtering block of the neural network.
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公开(公告)号：US20230146259A1
公开(公告)日：2023-05-11
申请号：US17980492
申请日：2022-11-03
Applicant: Intel Corporation
Inventor： Gabor Liktor , Karthik Vaidyanathan , Tobias Zirr
IPC: G06T3/40 , H04N13/271 , G06T3/00
CPC classification number: G06T3/4046 , G06T3/4053 , H04N13/271 , G06T3/0093
Abstract: Sampling across multiple views in supersampling operation is described. An example of an apparatus includes one or more processing resources configured to perform a supersampling operation for image data generated for multiple views utilizing one or more neural networks, the processing resources including at least a first circuitry to process a first current frame including first image data for a first view, and a second circuitry to process a second current frame including second image data for a second view, the first view and second view being displaced from each other, the processing resources to receive for processing the first current frame and the second current frame, and perform supersampling processing utilizing the one or more neural networks based on at least the first current frame and the second current frame and one or more prior generated frames for each of the views.
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