公开(公告)号：US12249622B2

公开(公告)日：2025-03-11

申请号：US16713684

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Rahul Ramaswamy ,  Jeong Dong Kim ,  Ting Chang ,  Walid M. Hafez ,  Babak Fallahazad ,  Hsu-Yu Chang ,  Nidhi Nidhi

IPC: H01L29/786 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  B82Y40/00

Abstract: Embodiments disclosed herein include nanowire and nanoribbon devices with non-uniform dielectric thicknesses. In an embodiment, the semiconductor device comprises a substrate and a plurality of first semiconductor layers in a vertical stack over the substrate. The first semiconductor layers may have a first spacing. In an embodiment, a first dielectric surrounds each of the first semiconductor layers, and the first dielectric has a first thickness. The semiconductor device may further comprise a plurality of second semiconductor layers in a vertical stack over the substrate, where the second semiconductor layers have a second spacing that is greater than the first spacing. In an embodiment a second dielectric surrounds each of the second semiconductor layers, and the second dielectric has a second thickness that is greater than the first thickness.

公开(公告)号：US11996403B2

公开(公告)日：2024-05-28

申请号：US16713656

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Ting Chang ,  Babak Fallahazad ,  Tanuj Trivedi ,  Jeong Dong Kim ,  Ayan Kar ,  Benjamin Orr

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0255 ,  H01L29/0673 ,  H01L29/66136

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a source. The source has a first conductivity type and a first insulator separates the source from the semiconductor substrate. The semiconductor device further comprises a drain. The drain has a second conductivity type that is opposite from the first conductivity type, and a second insulator separates the drain from the semiconductor substrate. In an embodiment, the semiconductor further comprises a semiconductor body between the source and the drain, where the semiconductor body is spaced away from the semiconductor substrate.

公开(公告)号：US11967615B2

公开(公告)日：2024-04-23

申请号：US15773536

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Hsu-Yu Chang ,  Neville L. Dias ,  Walid M. Hafez ,  Chia-Hong Jan ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/1054 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/161 ,  H01L29/165

Abstract: Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.

公开(公告)号：US11437483B2

公开(公告)日：2022-09-06

申请号：US16810156

申请日：2020-03-05

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Rahul Ramaswamy ,  Jeong Dong Kim ,  Babak Fallahazad ,  Hsu-Yu Chang ,  Ting Chang ,  Nidhi Nidhi ,  Walid M. Hafez

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

公开(公告)号：US11121040B2

公开(公告)日：2021-09-14

申请号：US16317265

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Everett S. Cassidy-Comfort ,  Joodong Park ,  Walid M. Hafez ,  Chia-Hong Jan ,  Rahul Ramaswamy ,  Neville L. Dias ,  Hsu-Yu Chang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/265 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L27/088 ,  H01L29/10 ,  H01L27/02

Abstract: An apparatus comprising at least one transistor in a first area of a substrate and at least one transistor in a second area, a work function material on a channel region of each of the at least one transistor, wherein an amount of work function material in the first area is different than an amount of work function material in the second area. A method comprising depositing a work function material and a masking material on at least one transistor body in a first area and at least one in a second area; removing less than an entire portion of the masking material so that the portion of the work function material that is exposed in the first area is different than that exposed in the second area; removing the exposed work function material; and forming a gate electrode on each of the at least one transistor bodies.

公开(公告)号：US11075286B2

公开(公告)日：2021-07-27

申请号：US16344003

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Neville L. Dias ,  Rahul Ramaswamy ,  Hsu-Yu Chang ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/08 ,  H01L29/10

Abstract: A transistor including a source and a drain each formed in a substrate; a channel disposed in the substrate between the source and drain, wherein the channel includes opposing sidewalls with a distance between the opposing sidewalls defining a width dimension of the channel and wherein the opposing sidewalls extend a distance below a surface of the substrate; and a gate electrode on the channel. A method of forming a transistor including forming a source and a drain in an area of a substrate; forming a source contact on the source and a drain contact on the drain; after forming the source contact and the drain contact, forming a channel in the substrate in an area between the source and drain, the channel including a body having opposing sidewalls separated by a length dimension; and forming a gate contact on the channel.

公开(公告)号：US10964690B2

公开(公告)日：2021-03-30

申请号：US16474896

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Roman W. Olac-Vaw ,  Walid M. Hafez ,  Chia-Hong Jan ,  Hsu-Yu Chang ,  Neville L. Dias ,  Rahul Ramaswamy ,  Nidhi Nidhi ,  Chen-Guan Lee

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L49/02

Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.

公开(公告)号：US10854607B2

公开(公告)日：2020-12-01

申请号：US16853545

申请日：2020-04-20

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M Hafez ,  Jeng-Ya David Yeh ,  Hsu-Yu Chang ,  Neville L Dias ,  Chanaka D Munasinghe

IPC: H01L27/092 ,  H01L21/82 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L29/06 ,  H01L29/08

Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.

公开(公告)号：US10763209B2

公开(公告)日：2020-09-01

申请号：US15327338

申请日：2014-08-19

Applicant: INTEL CORPORATION

Inventor： Roman Olac-Vaw ,  Walid Hafez ,  Chia-Hong Jan ,  Hsu-Yu Chang ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu ,  Neville Dias

IPC: H01L29/78 ,  H01L23/525 ,  H01L29/423 ,  H01L29/66 ,  G11C17/16 ,  H01L21/768 ,  H01L27/112

Abstract: A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.

公开(公告)号：US20200251471A1

公开(公告)日：2020-08-06

申请号：US16853545

申请日：2020-04-20

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Jeng-Ya David Yeh ,  Hsu-Yu Chang ,  Neville L. Dias ,  Chanaka D. Munasinghe

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.