公开(公告)号：US12087658B2

公开(公告)日：2024-09-10

申请号：US16889562

申请日：2020-06-01

Applicant: INTEL CORPORATION

Inventor： Pooya Tadayon ,  Joe Walczyk

IPC: H01L23/373 ,  H01L23/42 ,  H01L23/40

CPC classification number: H01L23/3733 ,  H01L23/3736 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/4006

Abstract: A hybrid thermal interface material (TIM) suitable for an integrated circuit (IC) die package assembly. The hybrid TIM may include a heat-spreading material having a high planar thermal conductivity, and a supplemental material having a high perpendicular thermal conductivity at least partially filling through-holes within the heat-spreading material. The hybrid TIM may offer a reduced effective spreading and vertical thermal resistance. The heat-spreading material may have high compressibility (low bulk modulus or low hardness), such as a carbon-based (e.g., graphitic) material. The supplemental material may be of a suitable composition for filling the through-hole. The heat-spreading material, once compressed by a force applied through an IC die package assembly, may have a thickness substantially the same as that of the supplemental material such that both materials make contact with the IC die package and a thermal solution.

公开(公告)号：US12080620B2

公开(公告)日：2024-09-03

申请号：US16912432

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Xavier Brun ,  Paul Diglio ,  Joe Walczyk ,  Sergio Antonio Chan Arguedas

IPC: H01L23/373 ,  B33Y70/00 ,  B33Y80/00

CPC classification number: H01L23/3735 ,  B33Y70/00 ,  B33Y80/00

Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a backside metallization layer on the backside surface of the integrated circuit device, wherein the backside metallization layer comprises a bond layer on the backside surface of the integrated circuit device, a high thermal conductivity layer on the bond layer, and a cap layer on the high thermal conductivity layer. The bond layer may be a layered stack comprising an adhesion promotion layer on the backside of the integrated circuit device and at one least metal layer. The high thermal conductivity layer may be an additively deposited material having a thermal conductivity greater than silicon, such as copper, silver, aluminum, diamond, silicon carbide, boron nitride, aluminum nitride, and combinations thereof.

公开(公告)号：US11656247B2

公开(公告)日：2023-05-23

申请号：US16473378

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ronald Michael Kirby ,  Erkan Acar ,  Joe Walczyk ,  Youngseok Oh ,  Justin M Huttula ,  Mohanraj Prabhugoud

IPC: G01R1/07 ,  G01R1/04 ,  G01R1/073

CPC classification number: G01R1/07357 ,  G01R1/0466

Abstract: A coaxial wire interconnect architecture and associated methods are described. In one example, the coaxial wire interconnect architecture is used in a test socket interconnect array. Flexible bends are formed in one or more of the coaxial wire interconnects to provide compliant connections to an electronic device during testing.

公开(公告)号：US11249113B2

公开(公告)日：2022-02-15

申请号：US17111298

申请日：2020-12-03

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Mark Bohr ,  Joe Walczyk

IPC: G01R1/073 ,  H01L23/48 ,  H01L23/32 ,  H01L21/48 ,  H01L21/027 ,  G01R31/28 ,  H01L23/14

Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.

公开(公告)号：US20210375716A1

公开(公告)日：2021-12-02

申请号：US16889562

申请日：2020-06-01

Applicant: INTEL CORPORATION

Inventor： Pooya Tadayon ,  Joe Walczyk

IPC: H01L23/373

Abstract: A hybrid thermal interface material (TIM) suitable for an integrated circuit (IC) die package assembly. The hybrid TIM may include a heat-spreading material having a high planar thermal conductivity, and a supplemental material having a high perpendicular thermal conductivity at least partially filling through-holes within the heat-spreading material. The hybrid TIM may offer a reduced effective spreading and vertical thermal resistance. The heat-spreading material may have high compressibility (low bulk modulus or low hardness), such as a carbon-based (e.g., graphitic) material. The supplemental material may be of a suitable composition for filling the through-hole. The heat-spreading material, once compressed by a force applied through an IC die package assembly, may have a thickness substantially the same as that of the supplemental material such that both materials make contact with the IC die package and a thermal solution.

公开(公告)号：US20210249375A1

公开(公告)日：2021-08-12

申请号：US16785014

申请日：2020-02-07

Applicant: INTEL CORPORATION

Inventor： Feras Eid ,  Joe Walczyk ,  Weihua Tang ,  Akhilesh Rallabandi ,  Marco Aurelio Cartas Ayala

IPC: H01L23/00

Abstract: An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

公开(公告)号：US20200025801A1

公开(公告)日：2020-01-23

申请号：US16586763

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Mark Bohr ,  Joe Walczyk

IPC: G01R1/073 ,  H01L23/14 ,  G01R31/28 ,  H01L21/027 ,  H01L21/48 ,  H01L23/32 ,  H01L23/48

Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.

公开(公告)号：US20170273176A1

公开(公告)日：2017-09-21

申请号：US15614182

申请日：2017-06-05

Applicant: Intel Corporation

Inventor： Youngseok Oh ,  Joe Walczyk

IPC: H05K1/02

CPC classification number: H05K1/0268 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/116 ,  H05K3/4046

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. In one such embodiment, an apparatus may include an electronic arrangement, a first die, and a second die coupled to the first die and the electronic arrangement. The electronic arrangement may include an opening. At least a portion of the die may occupy at least a portion of the opening in the electronic arrangement. Other embodiments including additional apparatuses and methods are described.