公开(公告)号：US20250112196A1

公开(公告)日：2025-04-03

申请号：US18478843

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Feras Eid ,  Johanna Swan ,  Adel Elsherbini ,  Thomas L. Sounart ,  Tushar Kanti Talukdar ,  Brandon M. Rawlings ,  Kimin Jun ,  Andrey Vyatskikh ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L23/373 ,  H01L23/38 ,  H01L23/433 ,  H01L23/538 ,  H10N19/00

Abstract: An embodiment discloses an electronic device, comprising an integrated circuit (IC) die, a mesa structure formed on the IC die, and a die bonded to the IC die through the mesa structure.

公开(公告)号：US20250112177A1

公开(公告)日：2025-04-03

申请号：US18374516

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Feras Eid ,  Thomas Sounart ,  Yi Shi ,  Michael Baker ,  Adel Elsherbini ,  Kimin Jun ,  Xavier Brun ,  Wenhao Li

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/786

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die backside surface and a surface of a structural substrate each include bonding regions surrounded by hydrophobic structures. A liquid droplet is applied to the die or structural substrate bonding region and the die is placed on the bonding region of the structural substrate. Capillary forces cause the die to self-align to the bonding region, and a bond is formed by evaporating the liquid and subsequent anneal. A hybrid bond is then formed between the opposing active surface of the die and a base substrate using wafer-to-wafer bonding. IC structures including the IC die and portions of the structural substrate and base substrate are segmented from the bonded wafers and assembled.

公开(公告)号：US20250112067A1

公开(公告)日：2025-04-03

申请号：US18478963

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Thomas L. Sounart ,  Feras Eid ,  Tushar Kanti Talukdar ,  Adel Elsherbini ,  Carlos Bedoya Arroyave ,  Johanna Swan

IPC: H01L21/67 ,  H01L21/56 ,  H01L21/683 ,  H01L21/762

Abstract: In one embodiment, a selective transfer process includes forming a layer of integrated circuit (IC) components on a first substrate. The method also includes dispensing liquid droplets into a subset of a plurality of areas of a second substrate, where the areas of the second substrate are defined by hydrophobic lines patterned to match a layout of the IC components on the first substrate. The method further includes partially bonding the first substrate to the second substrate, where a subset of the IC components on the first substrate are bonded to the liquid droplets on the second substrate (e.g., via capillary forces), and separating the first substrate from the second substrate. When the first substrate is separated from the second substrate, the subset of IC components is separated from the first substrate and remain on the second substrate.

公开(公告)号：US20250109221A1

公开(公告)日：2025-04-03

申请号：US18374530

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Wenhao Li ,  Veronica Strong ,  Feras Eid ,  Bhaskar Jyoti Krishnatreya

IPC: C08F20/18 ,  C08F22/10 ,  C09J133/10

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region surrounded by hydrophobic structures that include a cross-linked material. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet and a subsequent anneal. The cross-linked material hydrophobic structures contain the liquid droplet for alignment and are resistant to plasma treatment prior to bonding.

公开(公告)号：US20250108459A1

公开(公告)日：2025-04-03

申请号：US18478770

申请日：2023-09-29

Applicant: INTEL CORPORATION

Inventor： Andrey Vyatskikh ,  Feras Eid ,  Tushar Kanti Talukdar ,  Kimin Jun ,  Thomas L. Sounart ,  Jeffery D. Bielefeld ,  Grant M. Kloster ,  Carlos Bedoya Arroyave ,  Golsa Naderi ,  Adel Elsherbini

IPC: B23K26/40 ,  B23K26/53 ,  B23K101/40 ,  B23K103/00

Abstract: An embodiment discloses a method comprising receiving a substrate comprising a first layer, a second layer over the first layer, and a third layer over the second layer, the third layer comprising a plurality of integrated circuit (IC) components, and applying a laser to ablate portions of the first layer, wherein the second layer protects the third layer from cracking during application of the laser.

公开(公告)号：US12155372B2

公开(公告)日：2024-11-26

申请号：US17688065

申请日：2022-03-07

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H03H9/54 ,  H03H9/02 ,  H03H9/64

Abstract: Embodiments may relate to a die such as an acoustic wave resonator (AWR) die. The die may include a first filter and a second filter in the die body. The die may further include an electromagnetic interference (EMI) structure that surrounds at least one of the filters. Other embodiments may be described or claimed.

公开(公告)号：US12113048B2

公开(公告)日：2024-10-08

申请号：US18090801

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Feras Eid ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L24/17 ,  H01L24/24 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1703 ,  H01L2224/17135 ,  H01L2224/17136 ,  H01L2224/17177 ,  H01L2224/17181 ,  H01L2224/24146 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.

公开(公告)号：US20240274576A1

公开(公告)日：2024-08-15

申请号：US18632919

申请日：2024-04-11

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel A. Elsherbini ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/17 ,  H01L24/29 ,  H01L24/30 ,  H01L25/0652 ,  H01L2224/08225 ,  H01L2224/09177 ,  H01L2224/81

Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region including metal contacts that are distributed non-uniformly. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact.

公开(公告)号：US12040776B2

公开(公告)日：2024-07-16

申请号：US16526633

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Aleksandar Aleksov ,  Feras Eid ,  Georgios Dogiamis ,  Johanna M. Swan

IPC: H03H9/05 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18 ,  H03H9/58 ,  H10N30/87 ,  H10N30/88 ,  H10N39/00 ,  H01L23/498

CPC classification number: H03H9/0552 ,  H01L23/5385 ,  H01L24/16 ,  H01L25/18 ,  H01L25/50 ,  H03H9/58 ,  H10N30/875 ,  H10N30/883 ,  H10N39/00 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2924/19042

Abstract: Embodiments may relate to a radio frequency (RF) front-end module (FEM) that includes an acoustic wave resonator (AWR) die. The RF FEM may further include an active die coupled with the package substrate of the RF FEM. When the active die is coupled with the package substrate, the AWR die may be between the active die and the package substrate. Other embodiments may be described or claimed.

公开(公告)号：US12002745B2

公开(公告)日：2024-06-04

申请号：US17544693

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew J. Manusharow ,  Krishna Bharath ,  William J. Lambert ,  Robert L. Sankman ,  Aleksandar Aleksov ,  Brandon M. Rawlings ,  Feras Eid ,  Javier Soto Gonzalez ,  Meizi Jiao ,  Suddhasattwa Nad ,  Telesphor Kamgaing

IPC: H05K1/02 ,  H01F17/00 ,  H01F17/06 ,  H01F27/28 ,  H01F27/40 ,  H01F41/04 ,  H01G4/18 ,  H01G4/252 ,  H01G4/30 ,  H01G4/33 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66 ,  H01L49/02

CPC classification number: H01L23/49838 ,  H01F17/0006 ,  H01F27/2804 ,  H01F27/40 ,  H01F41/041 ,  H01G4/33 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/66 ,  H01L28/00 ,  H01L28/10 ,  H01L28/60 ,  H01F2027/2809 ,  H01L2223/6661

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.