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    PHYSICAL INTERFACE FOR A SERIAL INTERCONNECT
    22.
    发明申请
    PHYSICAL INTERFACE FOR A SERIAL INTERCONNECT 有权
    串行互连的物理接口

    公开(公告)号：US20160179710A1

    公开(公告)日：2016-06-23

    申请号：US14580918

    申请日：2014-12-23

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Daniel S. Froelich ,  Venkatraman Iyer ,  Michelle C. Jen ,  Rahul R. Shah ,  Eric M. Lee

    IPC: G06F13/16 ,  G06F13/42

    CPC classification number: G06F13/4068 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/385 ,  G06F13/4282

    Abstract: An apparatus that includes a physical interface for a serial interconnect is provided. The physical interface includes a buffer that is selectable to function as a drift buffer or an elastic buffer by a voltage level on a buffer control line. The physical interface also includes encoding logic that can be enabled or disabled by a voltage level on a logic control line. Further, the physical interface also includes and an ordered set generator that can be enabled or disabled by a voltage level on a communications control line.

    Abstract translation: 提供了一种包括用于串行互连的物理接口的装置。 物理接口包括缓冲器，其可选择用作缓冲器控制线上的电压电平的漂移缓冲器或弹性缓冲器。 物理接口还包括可由逻辑控制线上的电压电平启用或禁用的编码逻辑。 此外，物理接口还包括可以通过通信控制线上的电压电平启用或禁用的有序集发生器。

    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS
    25.
    发明申请
    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS 审中-公开

    公开(公告)号：US20190310959A1

    公开(公告)日：2019-10-10

    申请号：US16446996

    申请日：2019-06-20

    Applicant: INTEL CORPORATION

    Inventor： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC: G06F13/40 ,  G06F13/38 ,  G06F13/16 ,  G06F13/42

    Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

    Bimodal PHY for low latency in high speed interconnects
    26.
    发明授权
    Bimodal PHY for low latency in high speed interconnects 有权

    公开(公告)号：US10372657B2

    公开(公告)日：2019-08-06

    申请号：US15390648

    申请日：2016-12-26

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC: G06F13/00 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16 ,  G06F13/38

    Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The low pin count PIPE interface is configured to transfer register commands between the PHY and MAC blocks over the small set of wires in a time-multiplexed manner to support read and write access of the PHY and MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture when operating in a PIPE mode and a serialization and deserialization (SERDES) architecture when operating in a SERDES mode.

    High performance interconnect link state transitions
    27.
    发明授权
    High performance interconnect link state transitions 有权

    公开(公告)号：US10324882B2

    公开(公告)日：2019-06-18

    申请号：US15393631

    申请日：2016-12-29

    Applicant: Intel Corporation

    Inventor： William R. Halleck ,  Rahul R. Shah ,  Venkatraman Iyer

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F13/12

    Abstract: An exit pattern is sent to initiate exit from a partial width state, where only a portion of the available lanes of a link are used to transmit data and the remaining lanes are idle. The exit pattern is sent on the idle lanes, the exit pattern including an electrical ordered set (EOS), one or more fast training sequences (FTS), a start of data sequence (SDS), and a partial fast training sequence (FTSp). The SDS includes a byte number field to indicate a number of a bytes measured from a previous control interval of the link, and an end of the SDS is sent to coincide with a clean flit boundary on the active lanes. The partial width state is exited based on the exit pattern and data is sent on all available lanes following the exit from the partial width state.

    HIGH SPEED INTERCONNECT WITH CHANNEL EXTENSION
    28.
    发明申请
    HIGH SPEED INTERCONNECT WITH CHANNEL EXTENSION 审中-公开

    公开(公告)号：US20180191523A1

    公开(公告)日：2018-07-05

    申请号：US15394278

    申请日：2016-12-29

    Applicant: Intel Corporation

    Inventor： Rahul R. Shah ,  William R. Halleck ,  Fulvio Spagna ,  Venkatraman Iyer

    IPC: H04L12/407 ,  H04L12/933 ,  H04B3/36

    CPC classification number: H04B3/36 ,  G06F13/40 ,  H04L47/125

    Abstract: An apparatus includes an agent to facilitate communication in one of two or more modes, where a first of the two or more modes involves communication over links including a first number of lanes and a second of the two or more modes involves communication over links including a second number of lanes, and the first number is greater than the second number. The apparatus further includes a memory including data to indicate which of the two or modes applies to a particular link and a multiplexer to reverse lane numbering on links including either the first number of lanes or the second number of lanes.

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