公开(公告)号：US20240222438A1

公开(公告)日：2024-07-04

申请号：US18089945

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L29/26 ,  H01L29/36 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/26 ,  H01L29/36 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7787

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for designing and fabricating semiconductor packages that include transistors that include wide band gap materials, such as silicon carbide or gallium nitride. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222435A1

公开(公告)日：2024-07-04

申请号：US18089936

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Wilfred GOMES ,  Anand S. MURTHY ,  Tahir GHANI ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L29/16 ,  H01L21/02 ,  H01L27/105

CPC classification number: H01L29/1608 ,  H01L21/02447 ,  H01L21/02529 ,  H01L27/105

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use a SiC layer that is coupled with another layer that includes another material. The SiC layer may be an active layer that includes devices, such as transistors, that are coupled with devices that may be in the other layer. The SiC layer may be coupled with the other layer using fusion bonding, hybrid bonding, layer transfer, and/or bump and island formation techniques. Other embodiments may be described and/or claimed.

公开(公告)号：US20240215256A1

公开(公告)日：2024-06-27

申请号：US18088552

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES ,  Pushkar RANADE ,  Sagar SUTHRAM

IPC: H10B53/20 ,  H01L23/522 ,  H01L23/528 ,  H10B53/10 ,  H10B61/00

CPC classification number: H10B53/20 ,  H01L23/5226 ,  H01L23/5283 ,  H10B53/10 ,  H10B61/10 ,  H10B61/22

Abstract: Structures having backside capacitors are described. In an example, an integrated circuit structure includes a front side structure including a device layer having a plurality of select transistors, a plurality of metallization layers above the plurality of select transistors, and a plurality of vias below and coupled to the plurality of select transistors. A backside structure is below the plurality of vias of the device layer. The backside structure includes a memory layer coupled to the plurality of select transistors by the plurality of vias.

公开(公告)号：US20240215222A1

公开(公告)日：2024-06-27

申请号：US18088543

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Sagar SUTHRAM ,  Anand S. MURTHY ,  Pushkar RANADE ,  Wilfred GOMES

IPC: H10B12/00

CPC classification number: H10B12/315

Abstract: Structures having backside power delivery and signal routing for front side DRAM are described. In an example, an integrated circuit structure includes a front side structure including a dynamic random access memory (DRAM) layer having one or more capacitors over one or more transistors, and a plurality of metallization layers above the DRAM layer. A backside structure is below and coupled to the transistors of the DRAM layer, the backside structure including metal lines for power delivery and signal routing to the one or more transistors of the DRAM layer.

公开(公告)号：US20240008253A1

公开(公告)日：2024-01-04

申请号：US17855545

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES ,  Cory WEBER ,  Rishabh MEHANDRU ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10826

Abstract: Structures having memory access transistors with backside contacts are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a fin-based transistor, and a capacitor structure above the fin-based transistor of the device layer. A backside structure is below the front-side structure. The backside structure includes a conductive contact electrically connected to the fin-based transistor of the device layer.

公开(公告)号：US20240006531A1

公开(公告)日：2024-01-04

申请号：US17855573

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Rishabh MEHANDRU ,  Sagar SUTHRAM ,  Cory WEBER ,  Tahir GHANI ,  Anand S. MURTHY ,  Pushkar RANADE ,  Wilfred GOMES

IPC: H01L29/78 ,  H01L27/13 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L27/13 ,  H01L27/124 ,  H01L29/66666

Abstract: Structures having vertical transistors are described. In an example, an integrated circuit structure includes a channel structure on a drain contact layer, the channel structure having an opening extending there through. A gate dielectric layer is on a bottom and along sides of the opening, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. A source contact layer is on sides of a portion of the gate dielectric layer extending above the channel structure.

公开(公告)号：US20240006317A1

公开(公告)日：2024-01-04

申请号：US17855586

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Cory WEBER ,  Rishabh MEHANDRU ,  Wilfred GOMES ,  Sagar SUTHRAM

IPC: H01L23/528 ,  H01L23/535 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L23/5286 ,  H01L23/535 ,  H01L29/785 ,  H01L21/76898 ,  H01L27/0924 ,  H01L21/823871

Abstract: Structures having vertical keeper or power gate for backside power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of fin-based transistors, and a plurality of metallization layers above the fin-based transistors of the device layer. A backside structure is below the fin-based transistors of the device layer. The backside structure includes a ground metal line. One or more vertical gate all-around transistors is between the fin-based transistors of the device layer and the ground metal line of the backside structure.

公开(公告)号：US20240006305A1

公开(公告)日：2024-01-04

申请号：US17855017

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Anand S. MURTHY ,  Tahir GHANI ,  Rishabh MEHANDRU ,  Cory WEBER

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775

CPC classification number: H01L23/5226 ,  H01L23/5286 ,  H01L23/5329 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/775

Abstract: Structures having airgaps for backside signal routing or power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a first conductive line laterally spaced apart from a second conductive line by an air gap.