公开(公告)号：US20240006483A1

公开(公告)日：2024-01-04

申请号：US17855567

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Rishabh MEHANDRU ,  Anand S. MURTHY ,  Wilfred GOMES ,  Cory WEBER ,  Sagar SUTHRAM

IPC: H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L29/78618 ,  H01L29/78696 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/7851

Abstract: Structures having raised epitaxy on channel structure transistors are described. In an example, an integrated circuit structure includes a channel structure having multi-layer epitaxial source or drain structures thereon, the multi-layer epitaxial source or drain structures having a recess extending there through. A gate dielectric layer is on a bottom and along sides of the recess and laterally surrounded by the epitaxial source or drain structures. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below an uppermost surface of the gate dielectric layer.

公开(公告)号：US20230005526A1

公开(公告)日：2023-01-05

申请号：US17943044

申请日：2022-09-12

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  Abhishek SHARMA ,  Wilfred GOMES ,  Pushkar RANADE ,  Kuljit S. BAINS ,  Tahir GHANI ,  Anand MURTHY

IPC: G11C11/406 ,  H01L25/065 ,  H01L25/18

Abstract: A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power. Based on the differences in the memory, the memory controller can manage access to the memory device with adjusted control parameters based on lower leakage voltage for the memory cells and lower line resistance for the memory array.

公开(公告)号：US20240222520A1

公开(公告)日：2024-07-04

申请号：US18090822

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY ,  Pushkar RANADE

IPC: H01L29/786 ,  H01L23/48 ,  H01L27/088 ,  H01L29/06 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L29/78696 ,  H01L23/481 ,  H01L27/0886 ,  H01L29/0673 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: Structures having vertical shared gate high-drive thin film transistors are described. In an example, an integrated circuit structure includes a stack of alternating dielectric layers and metal layers. A trench is through the stack of alternating dielectric layers and metal layers. A semiconductor channel layer is along sides of the trench. A gate dielectric layer is along sides the semiconductor channel layer in the trench. A gate electrode is within sides of the gate dielectric layer.

公开(公告)号：US20240222271A1

公开(公告)日：2024-07-04

申请号：US18090828

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Pushkar RANADE ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY ,  Sagar SUTHRAM

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/528 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Structures having routing across layers of channel structures are described. In an example, an integrated circuit structure includes a first stack of horizontal nanowires along a vertical direction. A second stack of horizontal nanowires is along the vertical direction, the second stack of horizontal nanowires beneath the first stack of horizontal nanowires. A conductive routing layer extends laterally between the first stack of horizontal nanowires and the second stack of horizontal nanowires.

公开(公告)号：US20230420533A1

公开(公告)日：2023-12-28

申请号：US17851960

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Wilfred GOMES ,  Anand S. MURTHY ,  Tahir GHANI ,  Sagar SUTHRAM

IPC: H01L29/423 ,  H01L27/12 ,  H01L27/092 ,  H01L23/528 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L27/1203 ,  H01L27/092 ,  H01L23/528 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/66742

Abstract: Structures having AOI gates with routing across nanowires are described. In an example, an integrated circuit structure includes a stack of horizontal nanowires along a vertical direction. A gate stack is over the stack of horizontal nanowires and is surrounding a channel region of each of the horizontal nanowires, the gate stack having one or more cuts in the vertical direction.

公开(公告)号：US20230125041A1

公开(公告)日：2023-04-20

申请号：US18086584

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Christopher P. MOZAK ,  Sagar SUTHRAM ,  Randy B. OSBORNE ,  Don Douglas JOSEPHSON ,  Surhud KHARE

IPC: H10B80/00 ,  G11C11/408 ,  H01L23/528 ,  G06F12/06

Abstract: A memory chip stack is described. The memory chip stack includes memory chips having a first plurality of memory channels, where non-yielding ones of the memory channels are to be disabled during operation of the memory chip stack. The first plurality of memory channels have a second plurality of memory banks, where non-yielding ones of the memory banks within yielding ones of the memory channels are to be disabled during the operation of the memory chip stack.

公开(公告)号：US20240222276A1

公开(公告)日：2024-07-04

申请号：US18089877

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H05K1/18

CPC classification number: H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H05K1/181 ,  H05K2201/10159

Abstract: Structures having lookup table decoders for FPGAs with high DRAM transistor density are described. In an example, an integrated circuit structure includes a plurality of fins or nanowire stacks, individual ones of the plurality of fins or nanowire stacks having a longest dimension along a first direction. A plurality of gate structures is over the plurality of fins or nanowire stacks, individual ones of the plurality of gate structures having a longest dimension along a second direction, wherein the first direction is non-orthogonal to the second direction.

公开(公告)号：US20240103304A1

公开(公告)日：2024-03-28

申请号：US17954286

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  John HECK ,  Ling LIAO ,  Mengyuan HUANG ,  Wilfred GOMES ,  Pushkar RANADE ,  Abhishek Anil SHARMA

IPC: G02F1/025

CPC classification number: G02F1/025

Abstract: Embodiments disclosed herein include a photonics module and methods of forming photonics modules. In an embodiment, the photonics module comprises a waveguide, and a modulator adjacent to the waveguide. In an embodiment, the modulator comprises a PN junction with a P-doped region and an N-doped region, where the PN junction is vertically oriented so that the P-doped region is over the N-doped region.

公开(公告)号：US20240103216A1

公开(公告)日：2024-03-28

申请号：US17954292

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  John HECK ,  Ling LIAO ,  Mengyuan HUANG ,  Wilfred GOMES ,  Pushkar RANADE ,  Abhishek Anil SHARMA

IPC: G02B6/12 ,  H01L25/16

CPC classification number: G02B6/12004 ,  H01L25/167

Abstract: Embodiments disclosed herein include through silicon waveguides and methods of forming such waveguides. In an embodiment, a through silicon waveguide comprises a substrate, where the substrate comprises silicon. In an embodiment, a waveguide is provided through the substrate. In an embodiment, the waveguide comprises a waveguide structure. and a cladding around the waveguide structure.

公开(公告)号：US20230223096A1

公开(公告)日：2023-07-13

申请号：US18122038

申请日：2023-03-15

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Christopher P. MOZAK ,  Sagar SUTHRAM ,  Randy B. OSBORNE

IPC: G11C29/42 ,  G11C29/46 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/46 ,  G11C29/1201

Abstract: Methods and apparatus for configurable ECC (error correction code) mode in DRAM. Selected memory cells in the bank arrays of a DRAM device (e.g., die) are used to store ECC bits. A DRAM device (e.g., die) is configured to operate in a first mode in which an on-die ECC engine employs selected bits in the arrays of memory cells in the DRAM banks as ECC bits to perform ECC operations and to operate in a second mode under which the ECC bits are not employed for ECC operations by the ECC engine and made available for external use by a host. In the second mode, the repurposed ECC bits may comprise RAS bits used for RAS (Reliability, Serviceability, and Availability) operations and/or metabits comprising metadata used for other operations by the host.