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    Save-restore circuitry with metal-ferroelectric-metal devices
    24.
    发明授权
    Save-restore circuitry with metal-ferroelectric-metal devices 有权

    公开(公告)号：US10777250B2

    公开(公告)日：2020-09-15

    申请号：US16144896

    申请日：2018-09-27

    Applicant: Intel Corporation

    Inventor： Kaushik Vaidyanathan ,  Daniel H. Morris ,  Huichu Liu ,  Dileep J. Kurian ,  Uygar E. Avci ,  Tanay Karnik ,  Ian A. Young

    IPC: G11C11/22 ,  G06F1/3234 ,  G11C11/413 ,  G11C14/00

    Abstract: Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cross-coupled inverters to save the state of the bit node and/or bit bar node when an associated circuit block transitions to a sleep state, and restore the state of the bit node and/or bit bar node when the associated circuit block transitions from the sleep state to an active state. The save-restore circuitry may be used in a flip-flop circuit, a register file circuit, and/or another suitable type of circuit. The save-restore circuitry may include a transmission gate coupled between the bit node (or bit bar node) and an internal node, and an MFM device coupled between the internal node and a plate line. Other embodiments may be described and claimed.

    System, apparatus and method for simultaneous read and precharge of a memory
    26.
    发明授权
    System, apparatus and method for simultaneous read and precharge of a memory 有权

    公开(公告)号：US10559348B2

    公开(公告)日：2020-02-11

    申请号：US15980813

    申请日：2018-05-16

    Applicant: Intel Corporation

    Inventor： Lavanya Subramanian ,  Kaushik Vaidyanathan ,  Anant Nori ,  Sreenivas Subramoney ,  Tanay Karnik

    IPC: G11C7/00 ,  G11C11/4094 ,  G06F13/16 ,  G11C11/4093 ,  G11C11/4091

    Abstract: In one embodiment, an apparatus includes a memory array having a plurality of memory cells, a plurality of bitlines coupled to the plurality of memory cells, and a plurality of wordlines coupled to the plurality of memory cells. The memory array may further include a sense amplifier circuit to sense and amplify a value stored in a memory cell of the plurality of memory cells. The sense amplifier circuit may include: a buffer circuit to store the value, the buffer circuit coupled between a first internal node of the sense amplifier circuit and a second internal node of the sense amplifier circuit; and an equalization circuit to equalize the first internal node and the second internal node while the sense amplifier circuit is decoupled from the memory array. Other embodiments are described and claimed.

    NEAR MEMORY SPARSE MATRIX COMPUTATION IN DEEP NEURAL NETWORK
    30.
    发明申请
    NEAR MEMORY SPARSE MATRIX COMPUTATION IN DEEP NEURAL NETWORK 有权

    公开(公告)号：US20220101091A1

    公开(公告)日：2022-03-31

    申请号：US17550405

    申请日：2021-12-14

    Applicant: Intel Corporation

    Inventor： Srivatsa Rangachar Srinivasa ,  Jainaveen Sundaram Priya ,  Bradley A. Jackson ,  Ambili Vengallur ,  Dileep John Kurian ,  Tanay Karnik

    IPC: G06N3/04 ,  G06N3/063 ,  G06F7/523 ,  G06F7/50

    Abstract: A DNN accelerator includes a multiplication controller controlling whether to perform matrix computation based on weight values. The multiplication controller reads a weight matrix from a WRAM in the DNN accelerator and determines a row value for a row in the weight matrix. In an embodiment where the row value is one, a first switch sends a read request to the WRAM to read weights in the row and a second switch forms a data transmission path from an IRAM in the DNN accelerator to a PE in the DNN accelerator. The PE receives the weights and input data stored in the IRAM and performs MAC operations. In an embodiment where the row value is zero, the first and second switches are not triggered. No read request is sent to the WRAM and the data transmission path is not formed. The PE will not perform any MAC operations.

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