公开(公告)号：US12294368B2

公开(公告)日：2025-05-06

申请号：US17485119

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Dheeraj Subbareddy ,  Mahesh Kumashikar ,  Dheemanth Nagaraj ,  Rajesh Vivekanandham ,  Anshuman Thakur ,  Ankireddy Nalamalpu ,  Md Altaf Hossain ,  Atul Maheshwari

IPC: H03K19/177 ,  G06F15/78 ,  G06F30/34 ,  H03K19/17758 ,  H03K19/17796 ,  H03K19/08

Abstract: The present disclosure is directed to 3-D stacked architecture for Programmable Fabrics and Central Processing Units (CPUs). The 3-D stacked orientation enables reconfigurability of the fabric, and allows the fabric to function using coarse-grained and fine-grained acceleration for offloading CPU processing. Additionally, the programmable fabric may be able to function to interface with multiple other compute chiplet components in the 3-D stacked orientation. This enables multiple compute components to communicate without the need for offloading the data communications between the compute chiplets.

公开(公告)号：US20230342309A1

公开(公告)日：2023-10-26

申请号：US18216867

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Md Altaf Hossain ,  Lai Guan Tang ,  Mahesh Kumashikar ,  Ankireddy Nalamalpu

IPC: G06F13/10 ,  H01L25/065 ,  H01L23/538

CPC classification number: G06F13/102 ,  H01L25/0655 ,  H01L25/0652 ,  H01L23/538 ,  H01L24/14

Abstract: A circuit system includes a support device that has first and second conductors. The circuit system also includes first, second, and third integrated circuits that are coupled to the support device. The second integrated circuit includes a peripheral region. The peripheral region includes a third conductor coupled between the first and the second conductors. The circuit system is configured to transmit a signal from the first integrated circuit through the first conductor, the third conductor, and the second conductor to the third integrated circuit. The first and the third integrated circuits are positioned diagonally in the circuit system

公开(公告)号：US20230018793A1

公开(公告)日：2023-01-19

申请号：US17950728

申请日：2022-09-22

Applicant: Intel Corporation

Inventor： Md Altaf Hossain ,  Mahesh Kumashikar ,  Ankireddy Nalamalpu ,  Sreedhar Ravipalli

IPC: G06F30/327

Abstract: A processing integrated circuit includes a processing core comprising hard logic circuits and a programmable interface circuit configurable to exchange signals between an external terminal of the processing integrated circuit and the hard logic circuits in the processing core.

公开(公告)号：US20220326676A1

公开(公告)日：2022-10-13

申请号：US17852859

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Sreedhar Ravipalli ,  Mahesh Kumashikar ,  Md Altaf Hossain ,  Ankireddy Nalamalpu

IPC: G05B19/05 ,  G06F15/78

Abstract: A circuit system includes a processing circuit, an accelerator circuit, and a buffer circuit that stores packets of data and that is coupled to the processing circuit and to the accelerator circuit. The buffer circuit functions as a crossbar circuit by allowing each of the accelerator circuit and the processing circuit to access at least one of the packets of data stored in the buffer circuit during access to another one of the packets of data stored in the buffer circuit.

公开(公告)号：US20220334630A1

公开(公告)日：2022-10-20

申请号：US17849625

申请日：2022-06-25

Applicant: Intel Corporation

Inventor： Sreedhar Ravipalli ,  Mahesh Kumashikar ,  Md Altaf Hossain ,  Ankireddy Nalamalpu

IPC: G06F1/324 ,  G06F1/3206

Abstract: A circuit system includes an accelerator circuit and a compute circuit. The accelerator circuit generates a request in response to receiving packets of data. The accelerator circuit generates an indication of a low power state based on a reduced number of the packets of data being received. The compute circuit performs a processing operation for the accelerator circuit using the packets of data in response to receiving the request. The compute circuit comprises a power management circuit that decreases a supply voltage in the compute circuit and decreases a frequency of a clock signal in the compute circuit in response to the indication of the low power state from the accelerator circuit.

公开(公告)号：US11296681B2

公开(公告)日：2022-04-05

申请号：US16726020

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Steven Hsu ,  Simeon Realov ,  Mahesh Kumashikar ,  Ram Krishnamurthy

IPC: H03K3/00 ,  H03K3/037 ,  G01R31/3177 ,  H03K3/038 ,  H03K19/20

Abstract: A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

公开(公告)号：US20210194469A1

公开(公告)日：2021-06-24

申请号：US16726020

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Steven Hsu ,  Simeon Realov ,  Mahesh Kumashikar ,  Ram Krishnamurthy

IPC: H03K3/037 ,  H03K19/20 ,  H03K3/038 ,  G01R31/3177

Abstract: A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

公开(公告)号：US12007929B2

公开(公告)日：2024-06-11

申请号：US17067365

申请日：2020-10-09

Applicant: Intel Corporation

Inventor： Anshuman Thakur ,  Dheeraj Subbareddy ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Mahesh Kumashikar

IPC: G06F13/40

CPC classification number: G06F13/4068

Abstract: A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path.

公开(公告)号：US11983135B2

公开(公告)日：2024-05-14

申请号：US17033593

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Anshuman Thakur ,  Md Altaf Hossain ,  Mahesh Kumashikar ,  Kemal Aygün ,  Casey Thielen ,  Daniel Klowden ,  Sandeep B. Sane

IPC: G06F13/42 ,  G06F30/30 ,  G06F30/347

CPC classification number: G06F13/4221 ,  G06F13/4282 ,  G06F30/30 ,  G06F30/347 ,  G06F2213/0026

Abstract: Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.

公开(公告)号：US20240096810A1

公开(公告)日：2024-03-21

申请号：US18206840

申请日：2023-06-07

Applicant: Intel Corporation

Inventor： Md Altaf Hossain ,  Mahesh Kumashikar ,  Ankireddy Nalamalpu

IPC: H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L25/0652 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2224/16225

Abstract: A circuit system includes a support device having an interconnection conductor. The circuit system also includes first, second, and third integrated circuits that are mounted on the support device. The interconnection conductor couples the first integrated circuit to the third integrated circuit. The second integrated circuit is between the first integrated circuit and the third integrated circuit.