公开(公告)号：US09397019B2

公开(公告)日：2016-07-19

申请号：US14189938

申请日：2014-02-25

Applicant: INTEL IP CORPORATION

Inventor： Sven Albers ,  Sonja Koller ,  Thorsten Meyer ,  Georg Seidemann ,  Christian Geissler ,  Andreas Wolter

IPC: H01L23/02 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及集成电路（IC）封装，其包括具有与第一侧相对设置的第一侧和第二侧的管芯。 IC封装还可以包括封装模具的至少一部分并且具有与模具的第一侧相邻的第一表面的封装材料和与第一表面相对设置的第二表面。 在实施例中，第二表面可以被成形为使得IC封装的一个或多个横截面积比IC封装的一个或多个其它横截面积更薄。 可以描述和/或要求保护其他实施例。

公开(公告)号：US11410908B2

公开(公告)日：2022-08-09

申请号：US16018268

申请日：2018-06-26

Applicant: Intel IP Corporation

Inventor： Reinhard Mahnkopf ,  Sonja Koller ,  Andreas Wolter

IPC: H01L23/373 ,  H01L27/12 ,  H01L23/367 ,  H01L23/498 ,  H01L21/768 ,  H01L23/00

Abstract: Present disclosure relates to IC devices with thermal mitigation structures in the form of metal structures provided in a semiconductor material of a substrate on which active electronic devices are integrated (i.e., front-end metal structures). In one aspect, an IC device includes a substrate having a first face and a second face, where at least one active electronic device is integrated at the first face of the substrate. The IC device further includes at least one front-end metal structure that extends from the first face of the substrate into the substrate to a depth that is smaller than a distance between the first face and the second face. Providing front-end metal structures may enable improved cooling options because such structures may be placed in closer vicinity to the active electronic devices, compared to conventional thermal mitigation approaches.

公开(公告)号：US20200227388A1

公开(公告)日：2020-07-16

申请号：US16641241

申请日：2017-09-29

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Thomas Wagner ,  Andreas Wolter ,  Andreas Augustin ,  Sonja Koller ,  Thomas Ort ,  Reinhard Mahnkopf

IPC: H01L25/065 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.

公开(公告)号：US20200068711A1

公开(公告)日：2020-02-27

申请号：US16343961

申请日：2016-11-23

Applicant: Intel IP Corporation

Inventor： Andreas Wolter ,  Georg Seidemann ,  Klaus Reingruber ,  Thomas Wagner

IPC: H05K1/11 ,  H05K1/18 ,  H01L23/00 ,  H05K3/34

Abstract: Systems and methods are provide to form one or more pads on at least one surface associated with a portion of a component, for example, a component associated with a surface-mounted device (SMD). Further, the systems and methods are directed to providing metal (for example, copper, Cu) layers on the surface of one or more terminations (for example, solder termination pads) of an electrical component. In one embodiment, the metal layers include metal termination pads that are fabricated on a carrier layer; components can be soldered to these termination pads, then the components with the metal pads can be debonded from the carrier layer. As such, the solder terminations of the components can be covered by the metal pads.The disclosed systems and methods can permit or otherwise facilitate a wider selection and easy availability of the components to be electrically and/or mechanically connected to semiconductor packages.

公开(公告)号：US20190341371A1

公开(公告)日：2019-11-07

申请号：US16515979

申请日：2019-07-18

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC: H01L25/065 ,  H01L25/10 ,  H01L21/48 ,  H01L23/48 ,  H01L25/00

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

公开(公告)号：US20190121041A1

公开(公告)日：2019-04-25

申请号：US16090024

申请日：2016-03-28

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Marc Dittes ,  Andreas Wolter ,  Klaus Reingruber ,  Georg Seidemann ,  Christian Geissler ,  Thomas Wagner ,  Richard Patten

IPC: G02B6/42 ,  H01L23/00

Abstract: Embodiments of the disclosure are directed to a chip package that includes a base that includes a redistribution layer; an optical transducer circuit element on the base electrically connected to the redistribution layer; an optical element adjacent to the optical transducer circuit element and at an edge of the base; and an encasement encasing the optical transducer circuit element and a portion of the optical element, wherein one side of the optical element is exposed at an edge of the encasement and at the edge of the printed circuit board.

公开(公告)号：US10229858B2

公开(公告)日：2019-03-12

申请号：US15427984

申请日：2017-02-08

Applicant: Intel IP Corporation

Inventor： Thorsten Meyer ,  Andreas Wolter

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L21/683 ,  H01L23/522 ,  H01L25/18 ,  H01L23/525

Abstract: Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a semiconductor device package has a semiconductor substrate having circuitry formed on the substrate. A plurality of conductive connection pads are on the semiconductor substrate to connect to the circuitry. A post is on each of a subset of the connection pads, the posts being formed of a conductive material. A dielectric layer is over the semiconductor substrate including over the connection pads and the posts. Filled vias are over each connection pad that is not of the subset and over each post of the subset of the connection pads and a connector is over each filled via.

公开(公告)号：US20180374819A1

公开(公告)日：2018-12-27

申请号：US16063145

申请日：2015-12-18

Applicant: Intel IP Corporation

Inventor： Christian Geissler ,  Sven Albers ,  Georg Seidemann ,  Andreas Wolter ,  Klaus Reingruber ,  Thomas Wagner ,  Marc Dittes

IPC: H01L23/00 ,  H01L25/065

Abstract: A method includes aligning a wire with a package body having a contact pad and moving the wire through the package body to form electrical contact with the contact pad.

公开(公告)号：US20180331080A1

公开(公告)日：2018-11-15

申请号：US15776475

申请日：2015-12-21

Applicant: Intel IP Corporation

Inventor： Christian Geissler ,  Sven Albers ,  Georg Seidemann ,  Andreas Wolter ,  Klaus Reingruber ,  Thomas Wagner ,  Marc Dittes

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L25/16 ,  H01L21/568 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19011 ,  H01L2924/19105

Abstract: A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a first vertical dimension, a second electrical device component includes a second vertical dimension and a third electrical device component comprises a third vertical dimension. The first electrical device component and the second electrical device component are arranged side by side in the common package. Further, the third electrical device component is arranged on top of the first electrical device component in the common package. At least a part of the third electrical device component is arranged vertically between a front side level of the second electrical device component and a back side level of the second electrical device component.

公开(公告)号：US10121726B2

公开(公告)日：2018-11-06

申请号：US14839510

申请日：2015-08-28

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Christian Geissler ,  Alexandra Atzesdorfer ,  Sonja Koller

IPC: H01L23/373 ,  H01L23/36 ,  G06F1/20 ,  H01L23/427

Abstract: Embodiments of the present disclosure relate to a cooler for semiconductor devices. The semiconductor device may be electrically coupleable to a power source. The device may generate heat when the power source supplies power to the device during use of the device. The cooler may be coupled to one or more surfaces of the device. The cooler may include a hydrophilic material to adsorb water from ambient air. During operation of the device, the cooler may cool the device by conduction of heat away from the device to the cooler. The cooler may include water that is evaporated during use of the device to increase cooling capacity of the cooler. The cooler may be recharged with water from humidity in air when the device is not operated or operated at a lower power level. Other embodiments may be described and/or claimed.