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    Microelectronic packages and assemblies with improved flyby signaling operation
    22.
    发明授权
    Microelectronic packages and assemblies with improved flyby signaling operation 有权
    具有改进的flyby信号操作的微电子封装和组件

    公开(公告)号：US09595511B1

    公开(公告)日：2017-03-14

    申请号：US15153367

    申请日：2016-05-12

    Applicant: Invensas Corporation

    Inventor： Belgacem Haba ,  Zhuowen Sun ,  Javier A. Delacruz

    IPC: H01L23/02 ,  H01L25/10 ,  H01L27/108

    CPC classification number: H01L25/105 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C29/023 ,  G11C29/028 ,  H01L23/5386 ,  H01L24/24 ,  H01L2224/24175 ,  H01L2225/1035 ,  H01L2225/1064

    Abstract: A microelectronic unit includes microelectronic elements having memory storage arrays. First terminals and second terminals at a surface of the microelectronic unit are configured for connection with corresponding first and second sets of circuit panel contacts which are coupled with conductors of a common signaling bus on the circuit panel. Front surfaces of first and second microelectronic elements define a plurality of first planes at a substantial angle to a second plane defined by the major surface of the circuit panel. Each of a plurality of delay elements within the microelectronic unit is electrically coupled with a signaling path of the common signaling bus between one of the first terminals and a corresponding second terminal. In such way, the delay elements may reduce adverse effects of additive signal energy reflected from the microelectronic packages back towards the common signaling bus.

    Abstract translation: 微电子单元包括具有存储器存储阵列的微电子元件。 在微电子单元的表面处的第一端子和第二端子被配置为与相应的第一组和第二组电路板触点连接，这些电路板触点与电路板上的公共信号总线的导体耦合。 第一和第二微电子元件的前表面以与电路板的主表面限定的第二平面成大致角度限定多个第一平面。 微电子单元内的多个延迟元件中的每一个与第一端子之间的一个与相应的第二端子之间的公共信号总线的信令路径电耦合。 以这种方式，延迟元件可以减少从微电子封装反射到公共信号总线的附加信号能量的不利影响。

    Dielets on flexible and stretchable packaging for microelectronics
    23.
    发明授权
    Dielets on flexible and stretchable packaging for microelectronics 有权

    公开(公告)号：US11355443B2

    公开(公告)日：2022-06-07

    申请号：US16515417

    申请日：2019-07-18

    Applicant: Invensas Corporation

    Inventor： Shaowu Huang ,  Javier A. Delacruz

    IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

    Abstract: Dielets on flexible and stretchable packaging for microelectronics are provided. Configurations of flexible, stretchable, and twistable microelectronic packages are achieved by rendering chip layouts, including processors and memories, in distributed collections of dielets implemented on flexible and/or stretchable media. High-density communication between the dielets is achieved with various direct-bonding or hybrid bonding techniques that achieve high conductor count and very fine pitch on flexible substrates. An example process uses high-density interconnects direct-bonded or hybrid bonded between standard interfaces of dielets to create a flexible microelectronics package. In another example, a process uses high-density interconnections direct-bonded between native interconnects of the dielets to create the flexible microelectronics packages, without the standard interfaces.

    Apparatus For Non-Volatile Random Access Memory Stacks
    24.
    发明申请
    Apparatus For Non-Volatile Random Access Memory Stacks 有权

    公开(公告)号：US20210193624A1

    公开(公告)日：2021-06-24

    申请号：US17122149

    申请日：2020-12-15

    Applicant: Invensas Corporation

    Inventor： Javier A. Delacruz ,  Belgacem Haba ,  Rajesh Katkar ,  Pearl Po-Yee Cheng

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00

    Abstract: A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.

    Non-Volatile Dynamic Random Access Memory
    25.
    发明申请
    Non-Volatile Dynamic Random Access Memory 有权

    公开(公告)号：US20210118864A1

    公开(公告)日：2021-04-22

    申请号：US17070253

    申请日：2020-10-14

    Applicant: Invensas Corporation

    Inventor： Javier A. Delacruz ,  Pearl Po-Yee Cheng ,  David Edward Fisch

    IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00

    Abstract: The present disclosure provides for a stacked memory combining RAM and one or more layers of NVM, such as NAND. For example, a first layer of RAM, such as DRAM, is coupled to multiple consecutive layers of NAND using direct bonding interconnect (DBI®). Serialization and overhead that exists in periphery of the NVM may be stripped to manage the data stored therein. The resulting connections between the RAM and the NVM are high bandwidth, high pincount interconnects. Interconnects between each of the one or more layers of NVM are also very dense.

    Wire bonding method and apparatus for electromagnetic interference shielding
    28.
    发明授权
    Wire bonding method and apparatus for electromagnetic interference shielding 有权

    公开(公告)号：US10658302B2

    公开(公告)日：2020-05-19

    申请号：US15914617

    申请日：2018-03-07

    Applicant: Invensas Corporation

    Inventor： Shaowu Huang ,  Javier A. Delacruz

    IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56

    Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

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