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    Method for Reduced Load Memory Module
    22.
    发明申请
    Method for Reduced Load Memory Module 有权

    公开(公告)号：US20170212848A1

    公开(公告)日：2017-07-27

    申请号：US15481288

    申请日：2017-04-06

    Applicant: Invensas Corporation

    Inventor： Zhuowen Sun ,  Yong Chen

    IPC: G06F13/16 ,  G06F12/06

    CPC classification number: G06F13/1673 ,  G06F12/00 ,  G06F12/0623 ,  G06F13/1694 ,  G11C5/04 ,  G11C5/06 ,  G11C8/06 ,  G11C8/12 ,  H01L2224/4824 ,  H01L2924/15311

    Abstract: A method for reducing load in a memory module. In such a method, a plurality of memory chips are coupled to a circuit platform. Each memory chip of the plurality of memory chips each has a plurality of memory dies. At least one controller is coupled to the circuit platform and further coupled to the plurality of memory chips for communication with the plurality of memory dies thereof. The at least one controller is for receiving chip select signals to provide a plurality of rank select signals in excess of the chip select signals. The plurality of memory dies are coupled with wire bonds within the plurality of memory chips for a reduced load for coupling the circuit platform for communicating via a memory channel. The load is sufficiently reduced for having at least two instances of the memory module share the memory channel.

    Via structure for signal equalization
    23.
    发明授权
    Via structure for signal equalization 有权
    通道结构用于信号均衡

    公开(公告)号：US09583417B2

    公开(公告)日：2017-02-28

    申请号：US14206756

    申请日：2014-03-12

    Applicant: Invensas Corporation

    Inventor： Zhuowen Sun ,  Cyprian Emeka Uzoh ,  Yong Chen

    IPC: H01L23/48 ,  H01L23/532 ,  H01L23/498

    CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/53295 ,  H01L23/5384 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/11 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00

    Abstract: An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first surface. The first surface and the second surface define a thickness of the substrate. A via structure extends from the first surface of the substrate to the second surface of the substrate. The via structure has a first terminal at or proximate to the first surface and a second terminal at or proximate to the second surface provided by a conductive member of the via structure extending from the first terminal to the second terminal. A barrier layer of the via structure is disposed between at least a portion of the conductive member and the substrate. The barrier layer has a conductivity configured to offset a capacitance between the conductive member and the substrate when a signal is passed through the conductive member of the via structure.

    Abstract translation: 公开了一般涉及基板的装置。 在这种装置中，衬底具有与第一表面相对的第一表面和第二表面。 第一表面和第二表面限定基底的厚度。 通孔结构从衬底的第一表面延伸到衬底的第二表面。 通孔结构具有位于第一表面处或靠近第一表面的第一端子和位于第二表面处或靠近第二表面处的第二端子，该第二端子由从第一端子延伸到第二端子的通孔结构的导电构件提供。 通孔结构的阻挡层设置在导电部件的至少一部分和基板之间。 阻挡层具有被配置为当信号通过通孔结构的导电构件时抵消导电构件和衬底之间的电容的导电性。

    In-package fly-by signaling
    25.
    发明授权
    In-package fly-by signaling 失效
    包装内飞行信号

    公开(公告)号：US08723329B1

    公开(公告)日：2014-05-13

    申请号：US13833278

    申请日：2013-03-15

    Applicant: Invensas Corporation

    Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Yong Chen

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H05K7/1459 ,  G11C5/063 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/0655 ,  H01L2224/4824 ,  H01L2924/15311

    Abstract: In-package fly-by signaling can be provided in a multi-chip microelectronic package having address lines on a package substrate configured to carry address information to a first connection region on the substrate having a first delay from terminals of the package, and the address lines being configured to carry the address information beyond the first connection region to at least to a second connection region having a second delay from the terminals that is greater than the first delay. Address inputs of a first microelectronic element, e.g., semiconductor chip, can be coupled with each of the address lines at the first connection region, and address inputs of a second microelectronic element can be coupled with each of the address lines at the second connection region.

    Abstract translation: 可以在具有在封装衬底上的地址线的多芯片微电子封装中提供封装内的飞越信号，该封装衬底被配置为将地址信息传送到具有来自封装端子的第一延迟的衬底上的第一连接区域，并且地址 线路被配置为将地址信息超出第一连接区域至少至少具有来自大于第一延迟的端子的具有第二延迟的第二连接区域。 第一微电子元件（例如，半导体芯片）的地址输入可以与第一连接区域处的每个地址线耦合，并且第二微电子元件的地址输入可以在第二连接区域与每个地址线耦合 。

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