公开(公告)号：US20050041403A1

公开(公告)日：2005-02-24

申请号：US10958924

申请日：2004-10-05

Applicant: James Cady ,  James Wilder ,  David Roper ,  Russell Rapport ,  James Wehrly ,  Jeffrey Buchle

Inventor： James Cady ,  James Wilder ,  David Roper ,  Russell Rapport ,  James Wehrly ,  Jeffrey Buchle

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/49816 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00012

Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP integrated circuit and a support element CSP integrated circuit are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint. The flex circuit provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).

Abstract translation: 本发明将封装的集成电路堆叠成节省PWB或其他板表面积的模块。 本发明可以利用各种尺寸和配置的封装，其范围从具有许多触点的较大封装的基底元件到较小的封装，例如诸如DSBGA的裸片尺寸的封装。 在根据本发明设计的优选实施例中，基体元件CSP集成电路和支撑元件CSP集成电路通过具有图案化以选择性地连接两个CSP元件的至少两个导电层的柔性电路聚集。 连接到支撑元件的柔性电路的一部分折叠在基座元件上，以将支撑元件设置在基座元件上方，同时减小了总的占地面积。 柔性电路在模块和诸如印刷电路板（PWB）的应用环境之间提供热和电连接路径。

公开(公告)号：US20050009234A1

公开(公告)日：2005-01-13

申请号：US10913220

申请日：2004-08-06

Applicant: Julian Partridge ,  James Wehrly ,  Julian Dowden ,  David Roper ,  James Cady

Inventor： Julian Partridge ,  James Wehrly ,  Julian Dowden ,  David Roper ,  James Cady

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L21/44 ,  H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01327 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. Multiple numbers of CSPs may be stacked in accordance with the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. A form standard is disposed along a planar surface of a CSP. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. The form standard achieves a reduced profile after the CSP has been attached to the form standard. In addition, in constructing modules in accordance with some preferred modes of the invention, CSP contacts are reduced in height to create lower profile modules. Thus, low profile embodiments of the modules of the present invention are devised.

Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。 根据本发明可以堆叠多个CSP。 根据本发明设计的堆叠模块中采用的CSP与柔性电路连接。 形式标准沿着CSP的平面设置。 形式标准提供了一种物理形式，允许在采用标准连接柔性电路设计时，在广泛的CSP封装系列中发现许多变化的封装尺寸。 形式标准在CSP附加到表单标准之后实现了简化的简档。 此外，在根据本发明的一些优选模式构建模块时，CSP触点的高度减小以形成下部轮廓模块。 因此，设计了本发明的模块的低调实施例。

公开(公告)号：US20080094803A1

公开(公告)日：2008-04-24

申请号：US11961477

申请日：2007-12-20

Applicant: James Wehrly ,  James Wilder ,  Paul Goodwin ,  Mark Wolfe

Inventor： James Wehrly ,  James Wilder ,  Paul Goodwin ,  Mark Wolfe

IPC: H05K7/20

CPC classification number: H05K1/189 ,  H05K1/0203 ,  H05K1/11 ,  H05K1/181 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: Flexible circuitry is populated with integrated circuitry disposed along one or both of its major sides. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. The circuit-populated flexible circuitry is disposed about an edge of a rigid substrate thus placing the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on one or both sides of the substrate. The substrate form is preferably devised from thermally conductive materials and includes a high thermal conductivity core or area that is disposed proximal to higher thermal energy devices such as an AMB when the flex circuit is brought about the substrate. Other variations include thermally-conductive clips that grasp respective ICs on opposite sides of the module to further shunt heat from the ICs. Preferred extensions from the substrate body or substrate core encourage reduced thermal variations amongst the integrated circuits of the module.

Abstract translation: 灵活的电路填充有沿其主要侧面或其两侧设置的集成电路。 沿柔性电路分布的触点提供模块与应用环境之间的连接。 电路填充的柔性电路围绕刚性衬底的边缘设置，从而将集成电路放置在衬底的一侧或两侧，在衬底的一侧或两侧上具有一层或两层集成电路。 衬底形式优选地由导热材料设计，并且当柔性电路绕在衬底上时，包括设置在较高热能器件（例如AMB）附近的高导热性芯或区域。 其他变型包括将模块的相对侧上的相应IC夹持的导热夹子，以进一步从IC分流热量。 来自衬底主体或衬底芯的优选延伸部件促进模块集成电路之间的热变化减小。

公开(公告)号：US20080090329A1

公开(公告)日：2008-04-17

申请号：US11874775

申请日：2007-10-18

Applicant: James Wehrly

Inventor： James Wehrly

IPC: H01L21/58

CPC classification number: H01L25/105 ,  H01L21/4871 ,  H01L23/3114 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/5387 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/3511 ,  Y10T29/49169 ,  Y10T29/53209 ,  Y10T29/5327 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a precursor assembly devised as a component for a stacked circuit module in accordance with a preferred embodiment of the present invention, one or more stiffeners are disposed at least partially between a flex circuit and an integrated circuit. In a two-high stacked circuit module devised in accordance with a preferred embodiment of the present invention, an integrated circuit is stacked above a precursor assembly. The two integrated circuits are connected with the flex circuit of the precursor assembly. The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules.

公开(公告)号：US20080088003A1

公开(公告)日：2008-04-17

申请号：US11873351

申请日：2007-10-16

Applicant: James Wehrly

Inventor： James Wehrly

IPC: H01L23/48

CPC classification number: H01L25/105 ,  H01L21/4871 ,  H01L23/3114 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/5387 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/3511 ,  Y10T29/49169 ,  Y10T29/53209 ,  Y10T29/5327 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a precursor assembly devised as a component for a stacked circuit module in accordance with a preferred embodiment of the present invention, one or more stiffeners are disposed at least partially between a flex circuit and an integrated circuit. In a two-high stacked circuit module devised in accordance with a preferred embodiment of the present invention, an integrated circuit is stacked above a precursor assembly. The two integrated circuits are connected with the flex circuit of the precursor assembly. The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules.

Abstract translation: 本发明将集成电路堆叠成节省电路板表面积的模块。 在根据本发明的优选实施例设计为用于堆叠电路模块的部件的前驱体组件中，一个或多个加强件至少部分地设置在柔性电路和集成电路之间。 在根据本发明的优选实施例设计的两层叠层电路模块中，集成电路堆叠在前体组件的上方。 两个集成电路与前体组件的柔性电路连接。 本发明可以有益于模块中集成电路的多种配置和组合。

公开(公告)号：US20080067662A1

公开(公告)日：2008-03-20

申请号：US11941718

申请日：2007-11-16

Applicant: David Roper ,  Curtis Hart ,  James Wilder ,  Phill Bradley ,  James Cady ,  Jeff Buchle ,  James Wehrly

Inventor： David Roper ,  Curtis Hart ,  James Wilder ,  Phill Bradley ,  James Cady ,  Jeff Buchle ,  James Wehrly

IPC: H01L23/14 ,  H01L21/58 ,  H05K1/00

CPC classification number: H05K1/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An IC die and a flexible circuit structure are integrated into a lower stack element that can be stacked with either further integrated lower stack element iterations or with pre-packaged ICs in any of a variety of package types. A die is positioned above the surface of portions of a pair of flex circuits. Connection is made between the die and the flex circuitry. A protective layer is formed to protect the flex-connected die and its connection to the flex. Connective elements are placed along the flex circuitry to create an array of module contacts along the second side of the flex circuitry. The flex circuitry is positioned above the body-protected die to create an integrated lower stack element. The integrated lower stack element may be stacked either with iterations of the integrated lower stack element or with a pre-packaged IC to create a multi-element stacked circuit module.

Abstract translation: 集成电路芯片和柔性电路结构被集成到下层堆叠元件中，该堆叠元件可以进一步集成的下堆叠元件迭代或者以各种封装类型中的任何一种封装的预先封装的IC堆叠。 模具位于一对柔性电路的部分的表面上方。 在管芯和柔性电路之间进行连接。 形成保护层以保护弯曲连接的模具及其与柔性件的连接。 连接元件沿着柔性电路放置，以沿柔性电路的第二侧创建一组模块触点。 柔性电路位于身体保护的模具上方，以形成集成的下层叠元件。 集成的下堆叠元件可以通过集成的下堆叠元件的迭代或者与预先封装的IC堆叠以产生多元件堆叠电路模块。

公开(公告)号：US20070201208A1

公开(公告)日：2007-08-30

申请号：US11364489

申请日：2006-02-27

Applicant: Paul Goodwin ,  James Wehrly

Inventor： Paul Goodwin ,  James Wehrly

IPC: H05K7/20

CPC classification number: G11C5/00 ,  G06F1/20 ,  G11C5/143 ,  H01L23/427 ,  H01L23/473 ,  H01L2224/16 ,  H01L2224/73253

Abstract: A circuit module that includes a system for reducing thermal variation and cooling the circuit module. In preferred embodiments, the module includes a thermally-conductive rigid substrate having first and second lateral sides, an edge, and an integrated cooling component. The integrated cooling component reduces thermal variation and cools the circuit module. Flex circuitry populated with a plurality of ICs and exhibiting a connective facility that comprises plural contacts for use with an edge connector is wrapped about the edge of the thermally-conductive substrate. Heat from the plurality of ICs is thermally-conducted by the thermally-conductive substrate to the integrated cooling component.

公开(公告)号：US20070158795A1

公开(公告)日：2007-07-12

申请号：US11670396

申请日：2007-02-01

Applicant: James Wehrly

Inventor： James Wehrly

IPC: H01L23/495

CPC classification number: H01L23/5387 ,  G06K19/07732 ,  H01L23/5388 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allowed the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.

Abstract translation: 本发明提供了一种在存储卡中采用引线封装的存储器件的系统和方法。 引线封装IC布置在柔性电路结构的一侧或两侧以产生IC填充结构。 在优选实施例中，构成引线IC封装的引线被配置为允许引线IC封装的下表面接触柔性电路结构的相应表面。 用于典型实施例的触头由柔性电路结构的刚性部分支撑，并且IC填充结构设置在壳体中以为模块提供卡结构。

公开(公告)号：US20070117262A1

公开(公告)日：2007-05-24

申请号：US11626316

申请日：2007-01-23

Applicant: Julian Partridge ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly

Inventor： Julian Partridge ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly

IPC: H01L21/00

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/3463 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00

Abstract: The present invention provides a system and method that amounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.

Abstract translation: 本发明提供了一种将集成电路器件分配到衬底上的系统和方法，以及用于在堆叠模块中采用该方法的系统和方法。 封装的集成电路器件的接触焊盘基本上露出。 将包括较高温度的焊膏合金的焊膏施加到要安装的基板或集成电路器件上。 集成电路器件定位成与衬底的触点接触。 施加热量以在基板的触点和集成电路装置之间形成高温接头，从而形成具有高温接头的装置 - 基板组件。 形成的接头在随后的加工步骤中较少受到再熔化。 该方法可以用于设计堆叠的模块结构，例如根据本发明的优选实施例中公开的那些。 通常，创建的关节的轮廓较低。

公开(公告)号：US20060263938A1

公开(公告)日：2006-11-23

申请号：US11411185

申请日：2006-04-25

Applicant: Julian Partridge ,  James Wehrly ,  David Roper

Inventor： Julian Partridge ,  James Wehrly ,  David Roper

IPC: H01L21/00

CPC classification number: H05K3/3436 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/4985 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/189 ,  H05K3/305 ,  H05K2203/0278 ,  Y02P70/613 ,  H01L2224/0401

Abstract: A combination composed from a form standard and a CSP is attached to flex circuitry. Solder paste is applied to first selected locations on the flex circuitry and adhesive is applied to second selected locations on the flex circuitry. The flex circuitry and the combination of the form standard and CSP are brought into proximity with each other. During solder reflow operation, a force is applied that tends to bring the combination and flex circuitry closer together. As the heat of solder reflow melts the contacts of the CSP, the combination collapses toward the flex circuitry displacing the adhesive as the solder paste and contacts merge into solder joints. In a preferred embodiment, the form standard will be devised of heat transference material, a metal, for example, such as copper would be preferred, to improve thermal performance. In other embodiments, the methods of the invention may be used to attach a CSP without a form standard to flex circuitry.

Abstract translation: 由表单标准和CSP组合的组合连接到柔性电路。 将焊膏施加到柔性电路上的第一选定位置，并将粘合剂施加到柔性电路上的第二选定位置。 柔性电路和形式标准和CSP的组合彼此接近。 在回流焊接操作期间，施加的力将使组合和柔性电路更靠近在一起。 随着焊料回流的热量熔化CSP的触点，当焊膏和触点合并到焊点中时，组合朝向柔性电路折叠，使粘合剂移位。 在优选实施例中，将设计热转移材料的形式标准，优选金属，例如铜，以改善热性能。 在其他实施例中，本发明的方法可用于将没有形式标准的CSP连接到柔性电路。