公开(公告)号：US20210057394A1

公开(公告)日：2021-02-25

申请号：US16986919

申请日：2020-08-06

Applicant: Japan Display Inc.

Inventor： Hideaki ABE

IPC: H01L25/075 ,  H01L33/60

Abstract: A display device includes a substrate, a first pixel region including a first light emitting element group over the substrate, a second pixel region including a second light emitting element group over the substrate and adjacent to the first light emitting element group, and a partition wall between the first light emitting element group and the second light emitting element. A height of the partition wall is larger than heights of a plurality of emitting elements included in each of the first light emitting element group and the second light emitting element group.

公开(公告)号：US20150002759A1

公开(公告)日：2015-01-01

申请号：US14314362

申请日：2014-06-25

Applicant: Japan Display Inc.

Inventor： Yasushi NAKANO ,  Hitoshi KAWAGUCHI ,  Hideaki ABE

IPC: G06F3/041 ,  H05K1/11

CPC classification number: G06F3/0416 ,  G06F3/0412 ,  G06F2203/04102 ,  G06F2203/04103 ,  H05K1/117 ,  H05K1/189

Abstract: A terminal connection structure includes plural first connection terminals which are arranged side by side in one direction on a first circuit substrate, and plural second connection terminals which are arranged side by side in the one direction on a second resin circuit substrate overlappingly connected to the first circuit substrate and are respectively connected to the plural first connection terminals. Each of the plural second connection terminals includes plural first wirings extending in a direction crossing the one direction, and a second wiring connected to the plural first wirings and extending in the one direction. The second wiring is provided in a region where the second circuit substrate is overlapped and connected to the first circuit substrate.

Abstract translation: 端子连接结构包括在第一电路基板上沿一个方向并排设置的多个第一连接端子，以及在与第一电路基板重叠连接的第二树脂电路基板上沿一个方向并排配置的多个第二连接端子 并且分别连接到多个第一连接端子。 多个第二连接端子中的每一个包括沿与该一个方向交叉的方向延伸的多个第一布线，以及连接到多个第一布线并沿一个方向延伸的第二布线。 第二布线设置在第二电路基板重叠并连接到第一电路基板的区域中。

公开(公告)号：US20140029226A1

公开(公告)日：2014-01-30

申请号：US13943087

申请日：2013-07-16

Applicant: Japan Display Inc.

Inventor： Hideaki ABE ,  Yasushi NAKANO ,  Hitoshi KAWAGUCHI

IPC: H05K1/11

CPC classification number: H05K1/111 ,  G02F1/13454 ,  G02F1/13458 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00

Abstract: An integrated circuit chip includes first and second electrode terminals electrically connected to an internal circuit, and a dummy bump arranged between the first and second electrode terminals on a back surface thereof. A wiring pattern includes first lines electrically connected to the first electrode terminals below the back surface of the integrated circuit chip and extend in the direction toward a display region outside the integrated circuit chip, and second lines electrically connected to the second electrode terminals below the back surface of the integrated circuit chip and extend in the direction opposite to the display region outside the integrated circuit chip. The dummy bump is configured to avoid at least one of the electrical connection between the dummy bump and all of the first lines and all of the second lines and the electrical connection between the dummy bump and the internal circuit.

Abstract translation: 集成电路芯片包括电连接到内部电路的第一和第二电极端子，以及布置在第一和第二电极端子的背面上的虚设凸块。 布线图案包括与集成电路芯片的背面下方的第一电极端子电连接并且朝向集成电路芯片外部的显示区域的方向延伸的第一线，以及与背面的第二电极端子电连接的第二线路 集成电路芯片的表面，并且在与集成电路芯片外部的显示区域相反的方向上延伸。 虚拟凸块被配置为避免虚设凸起与所有第一线和所有第二线之间的电连接以及虚设凸起与内部电路之间的电连接中的至少一个。