公开(公告)号：US08250331B2

公开(公告)日：2012-08-21

申请号：US12493161

申请日：2009-06-26

Applicant: Koichi Yamada ,  Gad Sheaffer ,  Ali-Reza Adl-Tabatabai ,  Landy Wang ,  Martin Taillefer ,  Arun Kishan ,  David Callahan ,  Jan Gray ,  Vadim Bassin

Inventor： Koichi Yamada ,  Gad Sheaffer ,  Ali-Reza Adl-Tabatabai ,  Landy Wang ,  Martin Taillefer ,  Arun Kishan ,  David Callahan ,  Jan Gray ,  Vadim Bassin

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34 ,  G06F9/455 ,  G06F9/46

CPC classification number: G06F12/1045 ,  G06F12/0815

Abstract: Operating system virtual memory management for hardware transactional memory. A method may be performed in a computing environment where an application running on a first hardware thread has been in a hardware transaction, with transactional memory hardware state in cache entries correlated by memory hardware when data is read from or written to data cache entries. The data cache entries are correlated to physical addresses in a first physical page mapped from a first virtual page in a virtual memory page table. The method includes an operating system deciding to unmap the first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction.

Abstract translation: 硬件事务内存的操作系统虚拟内存管理。 可以在运行在第一硬件线程上的应用程序已经处于硬件事务中的计算环境中执行一种方法，当数据从数据高速缓存条目读取或写入数据高速缓存条目时，高速缓存条目中的事务性存储器硬件状态由存储器硬件相关联。 数据高速缓存条目与从虚拟存储器页表中的第一虚拟页面映射的第一物理页面中的物理地址相关联。 该方法包括决定取消映射第一虚拟页面的操作系统。 结果，操作系统从虚拟存储器页表移除第一虚拟页面到第一物理页面的映射。 结果，操作系统执行至少第一物理页丢弃事务存储器硬件状态的动作。 实施例可以进一步挂起内核模式下的硬件事务。 实施例可以进一步执行软页错误处理，而不中止硬件事务，在返回到用户模式时恢复硬件事务，甚至成功地提交硬件事务。

公开(公告)号：US08229907B2

公开(公告)日：2012-07-24

申请号：US12495582

申请日：2009-06-30

Applicant: Jan Gray ,  Martin Taillefer ,  Yosseff Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Michael Magruder ,  David Callahan

Inventor： Jan Gray ,  Martin Taillefer ,  Yosseff Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Michael Magruder ,  David Callahan

IPC: G06F7/00

CPC classification number: G06F17/30377

Abstract: Hardware assisted transactional memory system with open nested transactions. Embodiments include a system whereby hardware acceleration of transactions can be accomplished by implementing open nested transaction in hardware which respect software locks such that a top level transaction can be implemented in software, and thus not be limited by hardware constraints typical when using hardware transactional memory systems.

Abstract translation: 具有开放嵌套交易的硬件辅助事务内存系统。 实施例包括一种系统，其中可以通过在硬件中实现开放式嵌套事务来实现事务的硬件加速，这些交易涉及软件锁定，使得顶级事务可以以软件实现，因此不受硬件事务存储器系统典型的硬件约束的限制 。

公开(公告)号：US08196123B2

公开(公告)日：2012-06-05

申请号：US11821838

申请日：2007-06-26

Applicant: Martin Taillefer

Inventor： Martin Taillefer

IPC: G06F9/44

CPC classification number: G06F9/526 ,  G06F9/4488

Abstract: Various technologies and techniques are disclosed for providing an object model for transactional memory. The object model for transactional memory allows transactional semantics to be separated from program flow. Memory transaction objects created using the object model can live beyond the instantiating execution scope, which allows additional details about the memory transaction to be provided and controlled. Transactional memory can be supported even from languages that do not directly expose transactional memory constructs. This is made possible by defining the object model in one or more base class libraries and allowing the language that does not support transactional memory directly to use transactional memory through the object model.

Abstract translation: 公开了各种技术和技术来提供用于事务性存储器的对象模型。 事务内存的对象模型允许事务语义与程序流分离。 使用对象模型创建的内存事务对象可以超出实例执行范围，这允许提供和控制内存事务的更多细节。 即使不直接暴露事务内存结构的语言，也可以支持事务性内存。 这可以通过在一个或多个基类库中定义对象模型，并允许不支持事务内存的语言直接通过对象模型来使用事务内存。

公开(公告)号：US20110145637A1

公开(公告)日：2011-06-16

申请号：US12638181

申请日：2009-12-15

Applicant: Jan Gray ,  Martin Taillefer ,  Yossi Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Vinod Grover ,  Mike Magruder ,  Matt Tolton ,  Bratin Saha ,  Gad Sheaffer ,  Vadim Bassin

Inventor： Jan Gray ,  Martin Taillefer ,  Yossi Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Vinod Grover ,  Mike Magruder ,  Matt Tolton ,  Bratin Saha ,  Gad Sheaffer ,  Vadim Bassin

IPC: G06F12/00 ,  G06F12/08 ,  G06F11/14

CPC classification number: G06F12/0815 ,  G06F9/467 ,  G06F11/141

Abstract: In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在具有多个事务执行模式的无界事务存储器（UTM）系统中选择开始第一事务的第一事务执行模式的方法。 这些事务执行模式包括在处理器的高速缓冲存储器内执行的硬件模式，使用处理器的事务硬件执行的硬件辅助模式以及软件缓冲器，以及在没有事务性硬件的情况下执行的软件事务存储器（STM）模式。 如果在STM模式下没有执行等待事务，则可以将第一事务执行模式选择为硬件模式的最高执行模式，否则可以选择较低的执行模式。 描述和要求保护其他实施例。

公开(公告)号：US20110145530A1

公开(公告)日：2011-06-16

申请号：US12638031

申请日：2009-12-15

Applicant: Martin Taillefer ,  Gad Sheaffer

Inventor： Martin Taillefer ,  Gad Sheaffer

IPC: G06F12/14 ,  G06F12/08 ,  G06F11/07

CPC classification number: G06F11/3648

Abstract: One embodiment includes method acts for detecting race conditions. The method includes beginning a critical section, during which conflicting reads and writes should be detected to determine if a race condition has occurred. This is performed by executing at a thread one or more software instructions to place a software lock on data. As a result of executing one or more software instructions to place a software lock on data, several additional acts are performed. In particular, the thread places a software lock on the data locking the data for at least one of exclusive writes or reads by the thread. And, at a local cache memory local to the thread, the thread enters the thread's memory isolation mode enabling local hardware buffering of memory writes and monitoring of conflicting writes or reads to or from the cache memory to detect reads or writes by non-lock respecting agents.

Abstract translation: 一个实施例包括用于检测竞态条件的方法动作。 该方法包括开始关键部分，在此期间应检测到冲突的读取和写入，以确定是否发生了竞争条件。 这通过在线程执行一个或多个软件指令来执行以对软件锁定数据。 作为执行一个或多个软件指令以对数据进行软件锁定的结果，执行几个附加动作。 特别地，线程将软件锁定在锁定数据的数据上，用于线程的排他写入或读取中的至少一个。 而且，在线程本地的本地高速缓存中，线程进入线程的内存隔离模式，使本地硬件缓冲内存写入并监视与高速缓冲存储器冲突的写入或读取，以通过非锁定来检测读取或写入 代理商

公开(公告)号：US20100332807A1

公开(公告)日：2010-12-30

申请号：US12493167

申请日：2009-06-26

Applicant: Gad Sheaffer ,  Jan Gray ,  Martin Taillefer ,  Ali-Reza Adl-Tabatabai ,  Bratin Saha ,  Vadim Bassin ,  Robert Y. Geva ,  David Callahan

Inventor： Gad Sheaffer ,  Jan Gray ,  Martin Taillefer ,  Ali-Reza Adl-Tabatabai ,  Bratin Saha ,  Vadim Bassin ,  Robert Y. Geva ,  David Callahan

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/467 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859

Abstract: Performing non-transactional escape actions within a hardware based transactional memory system. A method includes at a hardware thread on a processor beginning a hardware based transaction for the thread. Without committing or aborting the transaction, the method further includes suspending the hardware based transaction and performing one or more operations for the thread, non-transactionally and not affected by: transaction monitoring and buffering for the transaction, an abort for the transaction, or a commit for the transaction. After performing one or more operations for the thread, non-transactionally, the method further includes resuming the transaction and performing additional operations transactionally. After performing the additional operations, the method further includes either committing or aborting the transaction.

Abstract translation: 在基于硬件的事务内存系统中执行非事务性转义操作。 一种方法包括处理器上的硬件线程，开始针对线程的基于硬件的事务。 所述方法还包括暂停所述基于硬件的事务并对所述线程执行非事务性的一个或多个操作，并且不受以下事务的影响：所述事务的事务监视和缓冲，所述事务的中止或者所述事务的中止 提交交易。 在对线程执行一个或多个操作之后，非事务性地，该方法还包括恢复事务并事务地执行附加操作。 执行附加操作后，该方法还包括提交或中止事务。

公开(公告)号：US20090006751A1

公开(公告)日：2009-01-01

申请号：US11823236

申请日：2007-06-27

Applicant: Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

Inventor： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC: G06F12/00

CPC classification number: G06F9/466 ,  G06F9/45504 ,  G06F9/45533 ,  G06F2209/521

Abstract: Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. A central processing unit is provided with the transactional memory hardware. Code backpatching can be facilitated by providing transactional memory hardware that supports a facility to maintain private memory state and an atomic commit feature. Changes made to certain code are stored in the private state facility. Backpatching changes are enacted by attempting to commit all the changes to memory at once using the atomic commit feature. An efficient call return stack can be provided by using transactional memory hardware. A call return cache stored in the private state facility captures a host address to return to after execution of a guest function completes. A direct-lookup hardware-based hash table is used for the call return cache.

Abstract translation: 公开了用于使用事务性存储器硬件来加速虚拟化或仿真的各种技术和技术。 中央处理单元设置有事务存储器硬件。 可以通过提供事务性存储器硬件来支持代码反向补丁，该硬件支持维护私有内存状态和原子提交功能的功能。 对某些代码所做的更改存储在私人状态设施中。 通过尝试使用原子提交功能一次性向内存提交所有更改来实现后期更改。 可以通过使用事务性存储器硬件来提供高效的回叫栈。 存储在私有状态设施中的调用返回缓存捕获主机地址以在执行客户机功能完成后返回。 直接查找基于硬件的哈希表用于调用返回缓存。

公开(公告)号：US20090006750A1

公开(公告)日：2009-01-01

申请号：US11823224

申请日：2007-06-27

Applicant: Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

Inventor： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC: G06F12/00

CPC classification number: G06F9/45533 ,  G06F9/45504 ,  G06F9/45516 ,  G06F9/466

Abstract: Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. State isolation can be facilitated by providing isolated private state on transactional memory hardware and storing the stack of a host that is performing an emulation in the isolated private state. Memory accesses performed by a central processing unit can be monitored by software to detect that a guest being emulated has made a self modification to its own code sequence. Transactional memory hardware can be used to facilitate dispatch table updates in multithreaded environments by taking advantage of the atomic commit feature. An emulator is provided that uses a dispatch table stored in main memory to convert a guest program counter into a host program counter. The dispatch table is accessed to see if the dispatch table contains a particular host program counter for a particular guest program counter.

Abstract translation: 公开了用于使用事务性存储器硬件来加速虚拟化或仿真的各种技术和技术。 通过在事务性存储器硬件上提供隔离的私有状态并将执行仿真的主机的堆栈存储在隔离的私有状态中，可以促进状态隔离。 由中央处理单元执行的存储器访问可以被软件监视，以检测被仿真的客户对其自己的代码序列进行了自我修改。 事务存储器硬件可以用于通过利用原子提交功能来促进多线程环境中的调度表更新。 提供了一个仿真器，它使用存储在主存储器中的调度表将客户机程序计数器转换为主机程序计数器。 访问调度表以查看分派表是否包含特定客户机程序计数器的特定主机程序计数器。

公开(公告)号：US07441012B2

公开(公告)日：2008-10-21

申请号：US11397482

申请日：2006-04-03

Applicant: John H. Palevich ,  Martin Taillefer

Inventor： John H. Palevich ,  Martin Taillefer

IPC: G06F15/16

CPC classification number: H04L67/06 ,  G06F17/30067 ,  G06F17/30902 ,  H04L67/02 ,  H04L67/34 ,  H04L69/04

Abstract: A method and system that combines efficient caching and buffering to provide a network file system, that may utilize data stored in one or more compressed image files of sequentially arranged byte stream data. As an application requests file opens and file reads of a file system, one or more drivers convert the block requests into HTTP: byte range requests or the like in order to retrieve the data from a remote server. As the data is received, it is reconverted and adjusted to match the application's request. Sequential block access patterns can be detected and used to request additional data in a single request, in anticipation of future block requests, thereby increasing efficiency. Local caching of received data, including caching after uncompressing received data that was compressed, further increases efficiency. A compressed file system format optimized for sequential access is also described that when used, further improves the efficient data access.

Abstract translation: 一种组合高效缓存和缓冲以提供网络文件系统的方法和系统，其可以利用存储在一个或多个顺序排列的字节流数据的压缩图像文件中的数据。 随着应用程序请求文件打开和文件系统的文件读取，一个或多个驱动程序将块请求转换为HTTP：字节范围请求等，以便从远程服务器检索数据。 随着数据的收到，它被重新转换和调整以匹配应用程序的请求。 可以检测顺序块访问模式并用于在单个请求中请求附加数据，以期望将来的块请求，从而提高效率。 接收到的数据的本地缓存（包括解压后的缓存）接收到的压缩数据进一步提高了效率。 还描述了针对顺序访问优化的压缩文件系统格式，当使用时，进一步提高了有效的数据访问。

公开(公告)号：US20080022068A1

公开(公告)日：2008-01-24

申请号：US11489079

申请日：2006-07-18

Applicant: Martin Taillefer

Inventor： Martin Taillefer

IPC: G06F12/00

CPC classification number: G06F12/1009 ,  G06F12/109

Abstract: Guest logical to physical translation is leveraged for host-side memory access. A contiguous portion of host physical address space is dedicated to the guest operating system. A reusable offset value may be calculated upon guest operating system initialization. Everything stored in the guest “physical” address space can be directly mapped to the contiguous portion of host physical address space using the reusable offset value, if necessary, thereby greatly reducing mapping complexity for both store and look-up operations.