公开(公告)号：US09043553B2

公开(公告)日：2015-05-26

申请号：US11823224

申请日：2007-06-27

Applicant: Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

Inventor： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC: G06F12/00 ,  G06F9/455 ,  G06F9/46

CPC classification number: G06F9/45533 ,  G06F9/45504 ,  G06F9/45516 ,  G06F9/466

Abstract: Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. State isolation can be facilitated by providing isolated private state on transactional memory hardware and storing the stack of a host that is performing an emulation in the isolated private state. Memory accesses performed by a central processing unit can be monitored by software to detect that a guest being emulated has made a self modification to its own code sequence. Transactional memory hardware can be used to facilitate dispatch table updates in multithreaded environments by taking advantage of the atomic commit feature. An emulator is provided that uses a dispatch table stored in main memory to convert a guest program counter into a host program counter. The dispatch table is accessed to see if the dispatch table contains a particular host program counter for a particular guest program counter.

公开(公告)号：US08473921B2

公开(公告)日：2013-06-25

申请号：US12646438

申请日：2009-12-23

Applicant: Martin Taillefer ,  Ali-Reza Adl-Tabatabai ,  Gad Sheaffer ,  Peter Lachner ,  Richard Wurdack ,  Darek Mihocka ,  Jan Gray

Inventor： Martin Taillefer ,  Ali-Reza Adl-Tabatabai ,  Gad Sheaffer ,  Peter Lachner ,  Richard Wurdack ,  Darek Mihocka ,  Jan Gray

IPC: G06F9/44

CPC classification number: G06F11/362 ,  G06F12/0817

Abstract: Debugging software in systems with architecturally significant processor caches. A method may be practiced in a computing environment. The method includes acts for debugging a software application, wherein the software application is configured to use one or more architecturally significant processor caches coupled to a processor. The method includes beginning execution of the software application. A debugger is run while executing the software application. The software application causes at least one of reads or writes to be made to the cache in an architecturally significant fashion. The reads or writes made to the cache in an architecturally significant fashion are preserved while performing debugging operations that would ordinarily disturb the reads or writes made to the cache in an architecturally significant fashion.

Abstract translation: 在具有架构上重要的处理器高速缓存的系统中调试软件。 可以在计算环境中实施一种方法。 该方法包括用于调试软件应用程序的动作，其中软件应用被配置为使用耦合到处理器的一个或多个架构上重要的处理器高速缓存。 该方法包括开始执行软件应用程序。 在执行软件应用程序时运行调试器。 软件应用程序使得以架构上显着的方式对缓存进行读取或写入中的至少一个。 以架构上显着的方式对高速缓存进行的读取或写入被保留，同时执行调整操作，这些调试操作通常会以建筑上重要的方式干扰对高速缓存的读取或写入。

公开(公告)号：US08392929B2

公开(公告)日：2013-03-05

申请号：US12638031

申请日：2009-12-15

Applicant: Martin Taillefer ,  Gad Sheaffer

Inventor： Martin Taillefer ,  Gad Sheaffer

IPC: G06F9/455

CPC classification number: G06F11/3648

Abstract: One embodiment includes method acts for detecting race conditions. The method includes beginning a critical section, during which conflicting reads and writes should be detected to determine if a race condition has occurred. This is performed by executing at a thread one or more software instructions to place a software lock on data. As a result of executing one or more software instructions to place a software lock on data, several additional acts are performed. In particular, the thread places a software lock on the data locking the data for at least one of exclusive writes or reads by the thread. And, at a local cache memory local to the thread, the thread enters the thread's memory isolation mode enabling local hardware buffering of memory writes and monitoring of conflicting writes or reads to or from the cache memory to detect reads or writes by non-lock respecting agents.

Abstract translation: 一个实施例包括用于检测竞态条件的方法动作。 该方法包括开始关键部分，在此期间应检测到冲突的读取和写入，以确定是否发生了竞争条件。 这通过在线程执行一个或多个软件指令来执行以对软件锁定数据。 作为执行一个或多个软件指令以对数据进行软件锁定的结果，执行几个附加动作。 特别地，线程将软件锁定在锁定数据的数据上，用于线程的排他写入或读取中的至少一个。 而且，在线程本地的本地高速缓存中，线程进入线程的内存隔离模式，使内存写入能够进行本地硬件缓冲，并监视与高速缓冲存储器冲突的写入或读取，以通过非锁定来检测读取或写入 代理商

公开(公告)号：US08365016B2

公开(公告)日：2013-01-29

申请号：US13307492

申请日：2011-11-30

Applicant: Jan Gray ,  Martin Taillefer ,  Yossi Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Vinod Grover ,  Mike Magruder ,  Matt Tolton ,  Bratin Saha ,  Gad Sheaffer ,  Vadim Bassin

Inventor： Jan Gray ,  Martin Taillefer ,  Yossi Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Vinod Grover ,  Mike Magruder ,  Matt Tolton ,  Bratin Saha ,  Gad Sheaffer ,  Vadim Bassin

IPC: G06F11/00

CPC classification number: G06F12/0815 ,  G06F9/467 ,  G06F11/141

Abstract: In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在具有多个事务执行模式的无界事务存储器（UTM）系统中选择开始第一事务的第一事务执行模式的方法。 这些事务执行模式包括在处理器的高速缓冲存储器内执行的硬件模式，使用处理器的事务硬件执行的硬件辅助模式以及软件缓冲器，以及在没有事务性硬件的情况下执行的软件事务存储器（STM）模式。 如果在STM模式下没有执行等待事务，则可以将第一事务执行模式选择为硬件模式的最高执行模式，否则可以选择较低的执行模式。 描述和要求保护其他实施例。

公开(公告)号：US20100332721A1

公开(公告)日：2010-12-30

申请号：US12493161

申请日：2009-06-26

Applicant: Koichi Yamada ,  Gad Sheaffer ,  Ali-Reza Adl-Tabatabai ,  Landy Wang ,  Martin Taillefer ,  Arun Kishan ,  David Callahan ,  Jan Gray ,  Vadim Bassin

Inventor： Koichi Yamada ,  Gad Sheaffer ,  Ali-Reza Adl-Tabatabai ,  Landy Wang ,  Martin Taillefer ,  Arun Kishan ,  David Callahan ,  Jan Gray ,  Vadim Bassin

IPC: G06F12/08

CPC classification number: G06F12/1045 ,  G06F12/0815

Abstract: Operating system virtual memory management for hardware transactional memory. A method may be performed in a computing environment where an application running on a first hardware thread has been in a hardware transaction, with transactional memory hardware state in cache entries correlated by memory hardware when data is read from or written to data cache entries. The data cache entries are correlated to physical addresses in a first physical page mapped from a first virtual page in a virtual memory page table. The method includes an operating system deciding to unmap the first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction.

Abstract translation: 硬件事务内存的操作系统虚拟内存管理。 可以在运行在第一硬件线程上的应用程序已经处于硬件事务中的计算环境中执行一种方法，当数据从数据高速缓存条目读取或写入数据高速缓存条目时，高速缓存条目中的事务性存储器硬件状态由存储器硬件相关联。 数据高速缓存条目与从虚拟存储器页表中的第一虚拟页面映射的第一物理页面中的物理地址相关联。 该方法包括决定取消映射第一虚拟页面的操作系统。 结果，操作系统从虚拟存储器页表移除第一虚拟页面到第一物理页面的映射。 结果，操作系统执行至少第一物理页丢弃事务存储器硬件状态的动作。 实施例可以进一步挂起内核模式下的硬件事务。 实施例可以进一步执行软页错误处理，而不中止硬件事务，在返回到用户模式时恢复硬件事务，甚至成功地提交硬件事务。

公开(公告)号：US20090006406A1

公开(公告)日：2009-01-01

申请号：US11824379

申请日：2007-06-29

Applicant: Martin Taillefer

Inventor： Martin Taillefer

IPC: G06F7/00

CPC classification number: G06F9/466

Abstract: Various technologies and techniques are disclosed for providing a transaction grouping feature for use in programs operating under a transactional memory system. The transaction grouping feature is operable to allow transaction groups to be created that contain related transactions. The transaction groups are used to enhance performance and/or operation of the programs. For example, different locking and versioning mechanisms can be used with different transaction groups. When running transactions, a hardware transactional memory execution mechanism can be used for one transaction group while a software transactional memory execution mechanism used for another transaction group.

Abstract translation: 公开了各种技术和技术，用于提供用于在事务存储器系统下操作的程序中的事务分组特征。 事务分组功能可操作以允许创建包含相关事务的事务组。 交易组用于增强程序的性能和/或操作。 例如，不同的锁定和版本控制机制可以与不同的事务组一起使用。 运行事务时，硬件事务内存执行机制可用于一个事务组，而另一个事务组则使用软件事务内存执行机制。

公开(公告)号：US20080199834A1

公开(公告)日：2008-08-21

申请号：US11675489

申请日：2007-02-15

Applicant: Martin Taillefer ,  Bruno Silva ,  Kenneth Dwight Krossa

Inventor： Martin Taillefer ,  Bruno Silva ,  Kenneth Dwight Krossa

IPC: G09B19/00

CPC classification number: A63F13/355 ,  A63F13/12 ,  A63F2300/538 ,  A63F2300/6063 ,  H04L67/38

Abstract: According to the present disclosure, users can have PC experiences on game consoles. For example, a game console can become a computing device dedicated to a server PC. PC capabilities, applications, programs, and even desktops can be remoted from the server PC to the game console, cached on the game console, and displayed on the game console display. Moreover, any devices native to either the server PC or the game console can be easily shared between the server PC and the console. Alternatively, a game console can be a concurrent computing device with a server PC, where only minimal content is stored on the gaming console, and minimal applications are remoted from the server PC to the game console. In either the dedicated or remoted case, various common features may be used, such as notifications sent from the server PC to the game console.

Abstract translation: 根据本公开，用户可以在游戏机上具有PC体验。 例如，游戏机可以成为专用于服务器PC的计算设备。 PC功能，应用程序，程序甚至桌面可以从服务器PC远程到游戏机，缓存在游戏机上，并显示在游戏机显示屏上。 此外，任何服务器PC或游戏机本机的设备都可以在服务器PC和控制台之间轻松共享。 或者，游戏控制台可以是具有服务器PC的并发计算设备，其中只有最少的内容被存储在游戏控制台上，并且将最少的应用从服务器PC远程到游戏控制台。 在专用或远程情况下，可以使用各种常见功能，例如从服务器PC发送到游戏控制台的通知。

公开(公告)号：US20070294707A1

公开(公告)日：2007-12-20

申请号：US11454215

申请日：2006-06-15

Applicant: Martin Taillefer ,  Stanley W. Adermann

Inventor： Martin Taillefer ,  Stanley W. Adermann

IPC: G06F9/46

CPC classification number: G06F9/5077 ,  G06F9/54

Abstract: Techniques for enhancing or replacing host operating system functionality by leveraging guest operating system functionality are disclosed. Incoming data is received from a computing resource of a host operating system, and, before the incoming data is transmitted to a higher-level module in the host operating system, the incoming data is intercepted by a set of one or more leveraged guest modules in a guest operating system. After intercepting the incoming data, the leveraged guest modules perform one or more operations on the incoming data. The leveraged guest modules may provide more advanced support and capabilities to perform these operations than any counterpart functionality in the host operating system. In addition to performing these operations, the leveraged guest modules also determine whether or not to return the incoming data to the host operating system.

公开(公告)号：US20070288228A1

公开(公告)日：2007-12-13

申请号：US11450233

申请日：2006-06-08

Applicant: Martin Taillefer ,  Bruno Silva ,  Stanley W. Adermann ,  Landon M. Dyer

Inventor： Martin Taillefer ,  Bruno Silva ,  Stanley W. Adermann ,  Landon M. Dyer

IPC: G06F9/455

CPC classification number: G06F9/45537

Abstract: A computing device hosts a virtual machine executing a guest that issues guest hardware requests by way of any of a plurality of paths. Such paths include a path to non-existent virtual hardware, where an emulator intercepts and processes such guest hardware request with a corresponding actual hardware command; a path to an instantiated operating system, where the instantiated operating system processes each such guest hardware request with a corresponding actual hardware request; and a path to device hardware, where the device hardware directly processes each such guest hardware request.

Abstract translation: 计算设备承载执行客户机的虚拟机，其通过多条路径中的任何路径发出客户机硬件请求。 这样的路径包括到不存在的虚拟硬件的路径，其中仿真器使用相应的实际硬件命令拦截并处理这样的访客硬件请求; 实例化操作系统的路径，其中实例操作系统用相应的实际硬件请求处理每个这样的客户硬件请求; 以及设备硬件的路径，其中设备硬件直接处理每个这样的客户机硬件请求。

公开(公告)号：US07080131B2

公开(公告)日：2006-07-18

申请号：US11010502

申请日：2004-12-13

Applicant: John H. Palevich ,  Martin Taillefer

Inventor： John H. Palevich ,  Martin Taillefer

IPC: G06F15/16

CPC classification number: H04L67/06 ,  G06F17/30067 ,  G06F17/30902 ,  H04L67/02 ,  H04L67/34 ,  H04L69/04

Abstract: A method and system that combines efficient caching and buffering to provide a network file system, that may utilize data stored in one or more compressed image files of sequentially arranged byte stream data. As an application requests file opens and file reads of a file system, one or more drivers convert the block requests into HTTP: byte range requests or the like in order to retrieve the data from a remote server. As the data is received, it is reconverted and adjusted to match the application's request. Sequential block access patterns can be detected and used to request additional data in a single request, in anticipation of future block requests, thereby increasing efficiency. Local caching of received data, including caching after uncompressing received data that was compressed, further increases efficiency. A compressed file system format optimized for sequential access is also described that when used, further improves the efficient data access.

Abstract translation: 一种组合高效缓存和缓冲以提供网络文件系统的方法和系统，其可以利用存储在一个或多个顺序排列的字节流数据的压缩图像文件中的数据。 随着应用程序请求文件打开和文件系统的文件读取，一个或多个驱动程序将块请求转换为HTTP：字节范围请求等，以便从远程服务器检索数据。 随着数据的收到，它被重新转换和调整以匹配应用程序的请求。 可以检测顺序块访问模式并用于在单个请求中请求附加数据，以期望将来的块请求，从而提高效率。 接收到的数据的本地缓存（包括解压后的缓存）接收到的压缩数据进一步提高了效率。 还描述了针对顺序访问优化的压缩文件系统格式，当使用时，进一步提高了有效的数据访问。