中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

27 records (took 0.015 seconds)

    SEMICONDUCTOR PACKAGE WITH TSV DIE
    21.
    发明申请
    SEMICONDUCTOR PACKAGE WITH TSV DIE 有权

    公开(公告)号：US20230116326A1

    公开(公告)日：2023-04-13

    申请号：US17938911

    申请日：2022-09-06

    Applicant: MEDIATEK INC.

    Inventor： Ya-Lun Yang ,  Wen-Chou Wu ,  Che-Hung Kuo

    IPC: H01L23/48 ,  H01L25/16 ,  H01L23/00 ,  H01L23/498

    Abstract: A semiconductor package includes a bottom package having a substrate and a semiconductor die mounted on a top surface of the substrate. The semiconductor die has an active surface and a rear surface coupled to the top surface of the substrate. The semiconductor die comprises through silicon vias. A top package is stacked on the bottom package. The top package comprises a memory component. A middle re-distribution layer (RDL) structure is disposed between the top package and the bottom package. The active surface of the semiconductor die is directly connected to the middle RDL structure through connecting elements. The memory component is electrically connected to the substrate via the interconnect structures of the middle RDL structure and the through silicon vias of the semiconductor die.

    SEMICONDUCTOR PACKAGE WITH REDUCED CONNECTION LENGTH
    22.
    发明申请
    SEMICONDUCTOR PACKAGE WITH REDUCED CONNECTION LENGTH 有权

    公开(公告)号：US20230050400A1

    公开(公告)日：2023-02-16

    申请号：US17866566

    申请日：2022-07-18

    Applicant: MEDIATEK INC.

    Inventor： Che-Hung Kuo ,  Chung-Min Yang

    IPC: H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31

    Abstract: A semiconductor package includes a logic die surrounded by a molding compound; a memory die disposed in proximity to the logic die; a plurality of vias around the logic die for electrically connecting the logic die to the memory die. Each of the plurality of vias has an oval shape or a rectangular shape when viewed from above. The vias have a horizontal pitch along a first direction and a vertical pitch along a second direction. The vertical pitch is greater than the horizontal pitch.

    LAND-SIDE SILICON CAPACITOR DESIGN AND SEMICONDUCTOR PACKAGE USING THE SAME
    23.
    发明申请
    LAND-SIDE SILICON CAPACITOR DESIGN AND SEMICONDUCTOR PACKAGE USING THE SAME 有权

    公开(公告)号：US20220130814A1

    公开(公告)日：2022-04-28

    申请号：US17494851

    申请日：2021-10-06

    Applicant: MEDIATEK INC.

    Inventor： Che-Hung Kuo ,  Yi-Jyun Lee

    IPC: H01L27/01 ,  H01L25/065

    Abstract: A semiconductor package includes a package substrate; a semiconductor die mounted on a top surface of the package substrate; a plurality of conductive elements disposed on a bottom surface of the package substrate; and a land-side silicon capacitor disposed on the bottom surface of the package substrate and surrounded by the plurality of conductive elements. The land-side silicon capacitor includes at least two silicon capacitor unit dies adjoined to each other with an integral scribe line region.

    SEMICONDUCTOR DEVICE
    24.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210193540A1

    公开(公告)日：2021-06-24

    申请号：US17190584

    申请日：2021-03-03

    Applicant: MediaTek Inc.

    Inventor： Nan-Cheng Chen ,  Che-Ya Chou ,  Hsing-Chih Liu ,  Che-Hung Kuo

    IPC: H01L23/31 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/48 ,  H01L23/482 ,  H01L25/04

    Abstract: A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.

Patent Agency Ranking