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    SET PULSE FOR PHASE CHANGE MEMORY PROGRAMMING
    21.
    发明申请
    SET PULSE FOR PHASE CHANGE MEMORY PROGRAMMING 有权
    设置脉冲进行相位改变记忆编程

    公开(公告)号：US20130242650A1

    公开(公告)日：2013-09-19

    申请号：US13886564

    申请日：2013-05-03

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Aswin Thiruvengadam ,  William Melton ,  Rich Fackenthal ,  Andrew Oen

    IPC: G11C13/00

    CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/0069

    Abstract: A memory device and method for programming the memory device, including a method for a melting phase change memory cell by applying an electronic signal at a first value and subsequently decreasing the signal value. The phase change memory cell can be substantially crystallized after the decrease in signal value.

    Abstract translation: 一种用于对存储器件进行编程的存储器件和方法，包括通过以第一值施加电子信号并随后减小信号值来解耦相变存储器单元的方法。 在信号值下降之后，相变存储单元可以基本上结晶。

    Management of error-handling flows in memory devices using probability data structure
    22.
    发明授权
    Management of error-handling flows in memory devices using probability data structure 有权

    公开(公告)号：US12032833B2

    公开(公告)日：2024-07-09

    申请号：US17943082

    申请日：2022-09-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Aswin Thiruvengadam ,  Vamsi Pavan Rayaprolu

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0679

    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including running sample data through each of a set of error-handling operations performed on data residing in a segment of the memory device in an existing order associated with a workload; obtaining error recovery data as a result of running the sample data; and determining an optimized order of the set of error-handling operations based on probability of error recovery and latency data, wherein the probability of error recovery is based on the error recovery data, and wherein the optimized order comprises an adjustment to an order of one or more error-handling operations of the set of error-handling operations in the existing order.

    MODEL FOR PREDICTING MEMORY SYSTEM PERFORMANCE
    23.
    发明公开
    MODEL FOR PREDICTING MEMORY SYSTEM PERFORMANCE 审中-公开

    公开(公告)号：US20240055046A1

    公开(公告)日：2024-02-15

    申请号：US17819567

    申请日：2022-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Vamsi Pavan Rayaprolu ,  Aswin Thiruvengadam

    IPC: G11C11/4096 ,  G11C11/4076 ,  G11C7/24

    CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G11C7/24

    Abstract: Methods, systems, and devices for a model for predicting memory system performance are described. A memory system may generate a set of read commands and perform a first set of read operations at a memory device according to the generated read commands. The memory system may generate information indicating a performance of the memory device based on the first set of read operations and may update one or more coefficients of a model that correlates the information with a change in a read window. In some cases, the memory system may model the change in a read window based on the information and update one or more parameters associated with read operations based on the modelled change in the read window. The memory system may perform a second set of read operations at the memory device using the one or more updated parameters.

    Analysis of memory sub-systems based on threshold distributions
    28.
    发明授权
    Analysis of memory sub-systems based on threshold distributions 有权

    公开(公告)号：US11295209B2

    公开(公告)日：2022-04-05

    申请号：US16722507

    申请日：2019-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Aswin Thiruvengadam ,  Daniel L. Lowrance ,  Joshua Phelps ,  Peter B. Harrington

    IPC: G11C29/00 ,  G06N3/08 ,  G06F11/22 ,  G06N3/04 ,  G06F11/00 ,  G11C29/50

    Abstract: Disclosed is a system comprising a memory component having a plurality of memory cells capable of being in a plurality of states, each state of the plurality of states corresponding to a value stored by the memory cell, and a processing device, operatively coupled with the memory component, to perform operations comprising: obtaining, for the plurality of memory cells, a plurality of distributions of threshold voltages, wherein each of the plurality of distributions corresponds to one of the plurality of states, classifying each of the plurality of distributions among one of a plurality of classes, generating a vector comprising a plurality of components, wherein each of the plurality of components represents the class of a respective one of the plurality of distributions, and processing, using a classifier, the generated vector to determine a likelihood that the memory component will fail within a target period of time.

    Trim setting determination for a memory device
    29.
    发明授权
    Trim setting determination for a memory device 有权

    公开(公告)号：US11264112B2

    公开(公告)日：2022-03-01

    申请号：US17111755

    申请日：2020-12-04

    Applicant: Micron Technology, Inc.

    Inventor： Aswin Thiruvengadam ,  Daniel L. Lowrance ,  Peter Feeley

    IPC: G11C29/00 ,  G11C29/02 ,  G06F12/02 ,  G11C16/10 ,  G11C29/44

    Abstract: Apparatuses and methods related to a memory system including a controller and an array of memory cells are provided. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.

    Management of test resources to perform testing of memory components under different temperature conditions
    30.
    发明授权
    Management of test resources to perform testing of memory components under different temperature conditions 有权

    公开(公告)号：US11257565B2

    公开(公告)日：2022-02-22

    申请号：US17147072

    申请日：2021-01-12

    Applicant: Micron Technology, Inc.

    Inventor： Aswin Thiruvengadam ,  Sivagnanam Parthasarathy ,  Daniel Scobee ,  Frederick Jensen

    IPC: G11C29/38 ,  G11C29/36 ,  G06F12/16 ,  G06F3/06 ,  G06F11/10 ,  G06F11/16

    Abstract: Filter information including a first temperature level and a second temperature level associated with a test process to be executed on one or more memory components is determined. Information associated with the test process is distributed to a first test component including a first set of memory components and a first temperature control component and a second test component including a second set of memory components and a second temperature control component. First feedback information associated with execution of the test process by the first test component at the first temperature level established by the first temperature control component is received. Second feedback information associated with execution of the test process by the second test component at the second temperature level established by the second temperature control component is received. Based on at least one of the first feedback information or the second feedback information, a failure of the test process executed using at least one of the first temperature level or the second temperature level is determined.

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