公开(公告)号：US20220020414A1

公开(公告)日：2022-01-20

申请号：US17414823

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov ,  Shanky Kumar Jain

IPC: G11C11/22 ,  G11C11/4091

Abstract: Methods, systems, and devices related to page policies for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may be configured to receive a read command for data stored in the memory array and transfer the data from the memory array to the signal development cache. The memory device may be configured to sense the data using an array of sense amplifiers. The memory device may be configured to write the data from the signal development cache back to the memory array based on one or more policies.

公开(公告)号：US20240329885A1

公开(公告)日：2024-10-03

申请号：US18634610

申请日：2024-04-12

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov ,  Shanky Kumar Jain

IPC: G06F3/06 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/10 ,  G11C8/08 ,  G11C11/22 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/546 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/1012 ,  G11C7/1063 ,  G11C7/109 ,  G11C8/08 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4096 ,  G06F2212/60 ,  G06F2212/608 ,  G06F2212/72 ,  G06F2212/7201

Abstract: Methods, systems, and devices related to signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may also include a controller configured to determine whether data associated with an address of the memory array is stored in one or more cache blocks of the signal development cache. As an example, the memory device may determine whether the data is stored in one or more cache blocks of the signal development cache based on mapping information associated with the address of the memory array.

公开(公告)号：US11948617B2

公开(公告)日：2024-04-02

申请号：US17677557

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov

IPC: G11C11/16 ,  G11C11/22

CPC classification number: G11C11/1659 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/221 ,  G11C11/225

Abstract: Methods, systems, and devices for a magnetic cache for a memory device are described. Magnetic storage elements (e.g., magnetic memory cells, such as spin-transfer torque (STT) memory cells or magnetic tunnel junction (MTJ) memory cells) may be configured to act as a cache for a memory array, where the memory array includes a different type of memory cells. The magnetic storage elements may be inductively coupled to access lines for the memory array. Based on this inductive coupling, when a memory value is written to or read from a memory cell of the array, the memory value may concurrently be written to a magnetic storage element based on associated current through an access line used to write or read the memory cell. Subsequent read requests may be executed by reading the memory value from the magnetic storage element rather than from the memory cell of the array.

公开(公告)号：US11934703B2

公开(公告)日：2024-03-19

申请号：US17846715

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov ,  Shanky Kumar Jain

IPC: G11C11/22 ,  G06F3/06 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/10 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/546 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/1012 ,  G11C7/1063 ,  G11C7/109 ,  G11C8/08 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4096 ,  G06F2212/60 ,  G06F2212/608 ,  G06F2212/72 ,  G06F2212/7201

Abstract: Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable read broadcast operations. A read broadcast may occur from the memory array to multiple locations of the signal development cache, for example via one or more multiplexers.

公开(公告)号：US20230197120A1

公开(公告)日：2023-06-22

申请号：US18084914

申请日：2022-12-20

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov

IPC: G11C7/06 ,  G11C11/22

CPC classification number: G11C7/06 ,  G11C11/221 ,  G11C11/2275 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2297

Abstract: Methods, systems, and devices for inductive energy harvesting and signal development for a memory device are described. One or more inductors may be included in or coupled with a memory device and used to provide current for various operations of the memory device based on energy harvested by the inductors. An inductor may harvest energy based on current being routed through the inductor or based on being inductively coupled with a second inductor through which current is routed. After harvesting energy, an inductor may provide current, and the current provided by the inductor may be used to drive access lines or otherwise as part of executing one or more operations at the memory device. Such techniques may improve energy efficiency or improve the drive strength of signals for the memory device, among other benefits.

公开(公告)号：US11656801B2

公开(公告)日：2023-05-23

申请号：US17736806

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Shanky Kumar Jain ,  Dmitri A. Yudanov

IPC: G06F12/00 ,  G06F3/06 ,  G11C11/22 ,  G11C11/4091 ,  G06F12/0875 ,  G11C7/08 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/0893 ,  G06F12/1045 ,  G11C11/406 ,  G11C8/08 ,  G06F12/0802

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/546 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/109 ,  G11C7/1012 ,  G11C7/1063 ,  G11C8/08 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/40603 ,  G06F2212/60 ,  G06F2212/608 ,  G06F2212/72 ,  G06F2212/7201

Abstract: Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.

公开(公告)号：US11557325B2

公开(公告)日：2023-01-17

申请号：US16941107

申请日：2020-07-28

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov

IPC: G11C7/06 ,  G11C11/22

Abstract: Methods, systems, and devices for inductive energy harvesting and signal development for a memory device are described. One or more inductors may be included in or coupled with a memory device and used to provide current for various operations of the memory device based on energy harvested by the inductors. An inductor may harvest energy based on current being routed through the inductor or based on being inductively coupled with a second inductor through which current is routed. After harvesting energy, an inductor may provide current, and the current provided by the inductor may be used to drive access lines or otherwise as part of executing one or more operations at the memory device. Such techniques may improve energy efficiency or improve the drive strength of signals for the memory device, among other benefits.

公开(公告)号：US20220391144A1

公开(公告)日：2022-12-08

申请号：US17846715

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov ,  Shanky Kumar Jain

IPC: G06F3/06 ,  G11C11/22 ,  G11C11/4091 ,  G06F12/0875 ,  G11C7/08 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/0893 ,  G06F12/1045 ,  G11C11/406 ,  G11C8/08 ,  G06F12/0802

Abstract: Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable read broadcast operations. A read broadcast may occur from the memory array to multiple locations of the signal development cache, for example via one or more multiplexers.

公开(公告)号：US11372595B2

公开(公告)日：2022-06-28

申请号：US17414297

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov ,  Shanky Kumar Jain

IPC: G11C11/22 ,  G06F3/06 ,  G11C11/4091 ,  G06F12/0875 ,  G11C7/08 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/0893 ,  G06F12/1045 ,  G11C11/406 ,  G11C8/08 ,  G06F12/0802

Abstract: Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable read broadcast operations. A read broadcast may occur from the memory array to multiple locations of the signal development cache, for example via one or more multiplexers.

公开(公告)号：US20220180912A1

公开(公告)日：2022-06-09

申请号：US17677557

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov

IPC: G11C11/16

Abstract: Methods, systems, and devices for a magnetic cache for a memory device are described. Magnetic storage elements (e.g., magnetic memory cells, such as spin-transfer torque (STT) memory cells or magnetic tunnel junction (MTJ) memory cells) may be configured to act as a cache for a memory array, where the memory array includes a different type of memory cells. The magnetic storage elements may be inductively coupled to access lines for the memory array. Based on this inductive coupling, when a memory value is written to or read from a memory cell of the array, the memory value may concurrently be written to a magnetic storage element based on associated current through an access line used to write or read the memory cell. Subsequent read requests may be executed by reading the memory value from the magnetic storage element rather than from the memory cell of the array.