公开(公告)号：US20220261191A1

公开(公告)日：2022-08-18

申请号：US17736806

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Shanky Kumar Jain ,  Dmitri A. Yudanov

IPC: G06F3/06 ,  G11C11/22 ,  G11C11/4091 ,  G06F12/0875 ,  G11C7/08 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/0893 ,  G06F12/1045 ,  G11C11/406 ,  G11C8/08 ,  G06F12/0802

Abstract: Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.

公开(公告)号：US20210398578A1

公开(公告)日：2021-12-23

申请号：US16908420

申请日：2020-06-22

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov

IPC: G11C11/16

Abstract: Methods, systems, and devices for a magnetic cache for a memory device are described. Magnetic storage elements (e.g., magnetic memory cells, such as spin-transfer torque (STT) memory cells or magnetic tunnel junction (MTJ) memory cells) may be configured to act as a cache for a memory array, where the memory array includes a different type of memory cells. The magnetic storage elements may be inductively coupled to access lines for the memory array. Based on this inductive coupling, when a memory value is written to or read from a memory cell of the array, the memory value may concurrently be written to a magnetic storage element based on associated current through an access line used to write or read the memory cell. Subsequent read requests may be executed by reading the memory value from the magnetic storage element rather than from the memory cell of the array.

公开(公告)号：US11709634B2

公开(公告)日：2023-07-25

申请号：US17834659

申请日：2022-06-07

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov ,  Shanky Kumar Jain

IPC: G11C11/22 ,  G11C7/08 ,  G11C7/10 ,  G11C11/4096 ,  G06F3/06 ,  G11C11/4091 ,  G06F12/0875 ,  G11C11/4074 ,  G11C11/408 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/0893 ,  G06F12/1045 ,  G11C11/406 ,  G11C8/08 ,  G06F12/0802

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/546 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/109 ,  G11C7/1012 ,  G11C7/1063 ,  G11C8/08 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/40603 ,  G06F2212/60 ,  G06F2212/608 ,  G06F2212/72 ,  G06F2212/7201

Abstract: Methods, systems, and devices related to multiplexed signal development in a memory device are described. In one example, an apparatus in accordance with the described techniques may include a set of memory cells, a sense amplifier, and a set of signal development components each associated with one or more memory cells of the set of memory cells. The apparatus may further include a selection component, such as a signal development component multiplexer, that is coupled with the set of signal development components. The selection component may be configured to selectively couple a selected signal development component of the set of signal development components with the sense amplifier, which may support examples of signal development during overlapping time intervals.

公开(公告)号：US11693599B2

公开(公告)日：2023-07-04

申请号：US17568467

申请日：2022-01-04

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov ,  Shanky Kumar Jain

IPC: G06F3/00 ,  G06F3/06 ,  G11C11/22 ,  G11C11/4091 ,  G06F12/0875 ,  G11C7/08 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/0893 ,  G06F12/1045 ,  G11C11/406 ,  G11C8/08 ,  G06F12/0802

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/546 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/109 ,  G11C7/1012 ,  G11C7/1063 ,  G11C8/08 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/40603 ,  G06F2212/60 ,  G06F2212/608 ,  G06F2212/72 ,  G06F2212/7201

Abstract: Methods, systems, and devices related to domain-based access in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory array may be organized according to domains, which may refer to various configurations or collections of access lines, and selections thereof, of different portions of the memory array. In various examples, a memory device may determine a plurality of domains for a received access command, or an order for accessing a plurality of domains for a received access command, or combinations thereof, based on an availability of the signal development cache.

公开(公告)号：US20230066051A1

公开(公告)日：2023-03-02

申请号：US17980546

申请日：2022-11-03

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov ,  Shanky Kumar Jain

IPC: G06F3/06 ,  G11C11/22 ,  G11C11/4091 ,  G06F12/0875 ,  G11C7/08 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/0893 ,  G06F12/1045 ,  G11C11/406 ,  G11C8/08 ,  G06F12/0802

Abstract: Methods, systems, and devices for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.

公开(公告)号：US11520529B2

公开(公告)日：2022-12-06

申请号：US17414296

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov ,  Shanky Kumar Jain

IPC: G11C11/22 ,  G06F3/06 ,  G11C11/4091 ,  G06F12/0875 ,  G11C7/08 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/0893 ,  G06F12/1045 ,  G11C11/406 ,  G11C8/08 ,  G06F12/0802

Abstract: Methods, systems, and devices related to signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.

公开(公告)号：US11282557B2

公开(公告)日：2022-03-22

申请号：US16908420

申请日：2020-06-22

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov

IPC: G11C11/16 ,  G11C11/22

Abstract: Methods, systems, and devices for a magnetic cache for a memory device are described. Magnetic storage elements (e.g., magnetic memory cells, such as spin-transfer torque (STT) memory cells or magnetic tunnel junction (MTJ) memory cells) may be configured to act as a cache for a memory array, where the memory array includes a different type of memory cells. The magnetic storage elements may be inductively coupled to access lines for the memory array. Based on this inductive coupling, when a memory value is written to or read from a memory cell of the array, the memory value may concurrently be written to a magnetic storage element based on associated current through an access line used to write or read the memory cell. Subsequent read requests may be executed by reading the memory value from the magnetic storage element rather than from the memory cell of the array.

公开(公告)号：US20240404567A1

公开(公告)日：2024-12-05

申请号：US18733153

申请日：2024-06-04

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov

IPC: G11C7/06 ,  G11C11/22

Abstract: Methods, systems, and devices for inductive energy harvesting and signal development for a memory device are described. One or more inductors may be included in or coupled with a memory device and used to provide current for various operations of the memory device based on energy harvested by the inductors. An inductor may harvest energy based on current being routed through the inductor or based on being inductively coupled with a second inductor through which current is routed. After harvesting energy, an inductor may provide current, and the current provided by the inductor may be used to drive access lines or otherwise as part of executing one or more operations at the memory device. Such techniques may improve energy efficiency or improve the drive strength of signals for the memory device, among other benefits.

公开(公告)号：US11989450B2

公开(公告)日：2024-05-21

申请号：US17415664

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov ,  Shanky Kumar Jain

IPC: G06F3/06 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/10 ,  G11C8/08 ,  G11C11/22 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/546 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/1012 ,  G11C7/1063 ,  G11C7/109 ,  G11C8/08 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4096 ,  G06F2212/60 ,  G06F2212/608 ,  G06F2212/72 ,  G06F2212/7201

Abstract: Methods, systems, and devices related to signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may also include a controller configured to determine whether data associated with an address of the memory array is stored in one or more cache blocks of the signal development cache. As an example, the memory device may determine whether the data is stored in one or more cache blocks of the signal development cache based on mapping information associated with the address of the memory array.

公开(公告)号：US20220300210A1

公开(公告)日：2022-09-22

申请号：US17834659

申请日：2022-06-07

Applicant: Micron Technology, Inc.

Inventor： Dmitri A. Yudanov ,  Shanky Kumar Jain

IPC: G06F3/06 ,  G11C11/22 ,  G11C11/4091 ,  G06F12/0875 ,  G11C7/08 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/0893 ,  G06F12/1045 ,  G11C11/406 ,  G11C8/08 ,  G06F12/0802

Abstract: Methods, systems, and devices related to multiplexed signal development in a memory device are described. In one example, an apparatus in accordance with the described techniques may include a set of memory cells, a sense amplifier, and a set of signal development components each associated with one or more memory cells of the set of memory cells. The apparatus may further include a selection component, such as a signal development component multiplexer, that is coupled with the set of signal development components. The selection component may be configured to selectively couple a selected signal development component of the set of signal development components with the sense amplifier, which may support examples of signal development during overlapping time intervals.