DRIVE STRENGTH CALIBRATION FOR MULTI-LEVEL SIGNALING

    公开(公告)号:US20220375518A1

    公开(公告)日:2022-11-24

    申请号:US17882478

    申请日:2022-08-05

    Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

    OFFSET CANCELLATION
    22.
    发明申请

    公开(公告)号:US20220172757A1

    公开(公告)日:2022-06-02

    申请号:US17669153

    申请日:2022-02-10

    Abstract: Systems, methods, and apparatuses for offset cancellation are described. A memory device may determine that a channel is in a state that interrupts an active termination of the channel and enable the calibration of a reference voltage (e.g., by the memory device). For example, a channel used for data communications with a second device (e.g., a controller) may initially be in a state of active termination. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting calibration signals on the channel and detecting an offset associated with a reference voltage. The memory device may use the detected offset and the reference voltage to identify signals transmitted to the memory device over the channel.

    Receive-side crosstalk cancelation
    23.
    发明授权

    公开(公告)号:US11119700B2

    公开(公告)日:2021-09-14

    申请号:US16809449

    申请日:2020-03-04

    Abstract: Methods, systems, and devices for receive-side crosstalk cancelation are described. A device that receives multiple signals over different transmission lines may include a circuit for canceling crosstalk. The circuit may include one or more capacitors or inductors that are coupled with the inputs of multiple receive circuits. The circuit may also include a set of resistors that are coupled with the receive circuits. In some cases, the device may dynamically configure the cancelation circuit to provide a particular bandwidth or strength of cancelation. In such cases, the device may configure the circuit autonomously or based on control information from another device.

    Training procedure for receivers associated with a memory device

    公开(公告)号:US10997095B2

    公开(公告)日:2021-05-04

    申请号:US16538329

    申请日:2019-08-12

    Abstract: Systems, apparatuses, and methods for training procedures on reference voltages and sampling times associated with symbols communicated with a memory device are described. The training procedures may be configured to compensate for variations that may occur in different symbols of a signal. For example, an individual training operation may be performed for each reference voltage within a first unit interval. These individual training operations may allow a reference voltage of the first unit interval to be positionable independent of other reference voltages in the same unit interval or in different unit intervals. In another example, an individual training operation may be performed for the sampling time associated with a reference voltage. These individual training operations may allow a sampling time associated with a reference voltage in the first unit interval to be positionable independent of other sampling times in the same unit interval or in different unit intervals.

    CONTROLLED HEATING OF A MEMORY DEVICE

    公开(公告)号:US20210089230A1

    公开(公告)日:2021-03-25

    申请号:US16579437

    申请日:2019-09-23

    Abstract: Methods, systems, and devices for controlled and mode-dependent heating of a memory device are described. In various examples, a memory device or an apparatus that includes a memory device may have circuitry configured to heat the memory device. The circuitry configured to heat the memory device may be activated, deactivated, or otherwise operated based on an indication of a temperature (e.g., of the memory device). In some examples, activating or otherwise operating the circuitry configured to heat the memory device may be based on an operating mode (e.g., of the memory device), which may be associated with certain access operations or operational states (e.g., of the memory device). Various operations or operating modes (e.g., of the memory device) may also be based on indications of a temperature (e.g., of the memory device).

    SIGNAL PATH BIASING IN A MEMORY SYSTEM
    26.
    发明申请

    公开(公告)号:US20200334172A1

    公开(公告)日:2020-10-22

    申请号:US16849740

    申请日:2020-04-15

    Abstract: Methods, systems, and devices for signal path biasing in an electronic system (e.g., a memory system) are described. In one example, a memory device, a host device, or both may be configured to bias a signal path, between an idle state and an information transfer or between an information transfer and an idle state, to an intermediate or mid-bias voltage level, which may reduce signal interference associated with such transitions. In various examples, the described biasing to a voltage, such as a mid-bias voltage, may be associated with an access command or other command for information to be communicated between devices of the electronic system, such as a command for information to be communicated between a memory device and a host device.

    Transmission failure feedback schemes for reducing crosstalk

    公开(公告)号:US12124329B2

    公开(公告)日:2024-10-22

    申请号:US18211472

    申请日:2023-06-19

    CPC classification number: G06F11/1044 G06F11/1016 G06F11/1028 G11C29/42

    Abstract: Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

    Multi-driver signaling
    28.
    发明授权

    公开(公告)号:US12087393B2

    公开(公告)日:2024-09-10

    申请号:US17719486

    申请日:2022-04-13

    CPC classification number: G11C7/1084 G11C7/1057

    Abstract: Methods, systems, and devices for multi-driver signaling are described. An apparatus may include a first voltage source configured to supply a positive voltage and a second voltage source configured to supply a negative voltage. The apparatus may also include a first driver configured to couple a transmission line of a bus with the first voltage source and a second driver configured to couple the transmission line of the bus with the second voltage source. The first driver may be configured to transfer current to the transmission line based on a configurable resistance of the first driver. And the second driver configured to transfer current from the transmission line of the bus based on a configurable resistance of the second driver.

    Tracking a reference voltage after boot-up

    公开(公告)号:US12086005B2

    公开(公告)日:2024-09-10

    申请号:US17729813

    申请日:2022-04-26

    CPC classification number: G06F1/28 G06F1/206

    Abstract: Methods, systems, and devices for tracking a reference voltage (also referred to as VREFD) after boot-up are described. For example, a host device or a memory device may determine a temperature value associated with the memory device. The host device or the memory device may select a reference voltage offset value for the memory device based on mapping the temperature value associated with the memory device to a relationship between reference voltage offset values and temperature differential values associated with the memory device. The host device or the memory device may adjust a reference voltage value associated with the memory device based on the reference voltage offset value. The host device, or the memory device, may operate the memory device in accordance with the reference voltage value based on adjusting the reference voltage value.

    Offset cancellation
    30.
    发明授权

    公开(公告)号:US12027231B2

    公开(公告)日:2024-07-02

    申请号:US17669153

    申请日:2022-02-10

    Abstract: Systems, methods, and apparatuses for offset cancellation are described. A memory device may determine that a channel is in a state that interrupts an active termination of the channel and enable the calibration of a reference voltage (e.g., by the memory device). For example, a channel used for data communications with a second device (e.g., a controller) may initially be in a state of active termination. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting calibration signals on the channel and detecting an offset associated with a reference voltage. The memory device may use the detected offset and the reference voltage to identify signals transmitted to the memory device over the channel.

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