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    PASS VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE
    22.
    发明公开
    PASS VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240203513A1

    公开(公告)日：2024-06-20

    申请号：US18528178

    申请日：2023-12-04

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou

    IPC: G11C16/34 ,  G11C16/10 ,  G11C29/02

    CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/3495 ,  G11C29/022

    Abstract: A request to perform a program operation on a set of vertically stacked memory cells of a memory device is received. A pass voltage adjustment value based on a number of program erase cycles (PECs) associated with the memory device is determined responsive to determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable. A default pass voltage is adjusted by the pass voltage adjustment value to generate an adjusted pass voltage. The program operation on the set of vertically stacked memory cells is performed using the adjusted pass voltage.

    Selective data pattern write scrub for a memory system
    23.
    发明授权
    Selective data pattern write scrub for a memory system 有权

    公开(公告)号：US11929127B2

    公开(公告)日：2024-03-12

    申请号：US17463207

    申请日：2021-08-31

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhongguang Xu ,  Murong Lang ,  Zhenming Zhou

    IPC: G11C16/34

    CPC classification number: G11C16/3495 ,  G11C16/3404

    Abstract: A system includes a memory device having a plurality of memory cells and a processing device operatively coupled to the memory device. The processing device is to determine to perform a rewrite on at least a portion of the plurality of memory cells. The processing device can determine that a number of rewrite operations at first subset of memory cells storing a first logic state fail to satisfy a threshold criterion. The processing device can also cause a rewrite of data stored at a second subset of memory cells storing a second logic state in response to determining the number of rewrite operations performed at the first subset of memory cells fail to satisfy the threshold criterion.

    LOW STRESS REFRESH ERASE IN A MEMORY DEVICE
    26.
    发明公开
    LOW STRESS REFRESH ERASE IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240062827A1

    公开(公告)日：2024-02-22

    申请号：US18234289

    申请日：2023-08-15

    Applicant: Micron Technology, Inc.

    Inventor： Ronit Roneel Prakash ,  Pitamber Shukla ,  Ching-Huang Lu ,  Murong Lang ,  Zhenming Zhou

    IPC: G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

    CPC classification number: G11C16/16 ,  G11C16/3445 ,  G11C16/102 ,  G11C16/26

    Abstract: A memory device can include a memory device coupled with a processing device. The processing device causes a first erase operation to be performed at a block, where the first erase operation causes a pre-program voltage and a first erase voltage having a first magnitude to be applied to the block. The processing device causes an erase detection operation to be performed at the block. The processing device determines that the block fails to satisfy the erase detection operation responsive to causing the erase detection operation to be performed. The processing device further causes a second erase operation to be performed at the block responsive to determining that the block failed the erase detection operation, where the second erase operation causes a second erase voltage having a second magnitude to be applied to the block.

    Managing a hybrid error recovery process in a memory sub-system
    29.
    发明授权
    Managing a hybrid error recovery process in a memory sub-system 有权

    公开(公告)号：US11861178B2

    公开(公告)日：2024-01-02

    申请号：US17462605

    申请日：2021-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Zhongguang Xu ,  Jian Huang ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0679

    Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is receive. A request type associated with the memory access operation is determined. In response to determining that the request type associated with the request type associated with the memory access operation is a first request type, an error recovery operation associated with the first request type is performed. In response to determining that the request type associated with the memory access operation is a second request type, an error recovery operation associated with the second request type is performed.

    DYNAMIC READ LEVEL TRIM SELECTION FOR SCAN OPERATIONS OF MEMORY DEVICES
    30.
    发明公开
    DYNAMIC READ LEVEL TRIM SELECTION FOR SCAN OPERATIONS OF MEMORY DEVICES 审中-公开

    公开(公告)号：US20230393777A1

    公开(公告)日：2023-12-07

    申请号：US17830802

    申请日：2022-06-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yu-Chung Lien ,  Li-Te Chang ,  Zhenming Zhou

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0679

    Abstract: A first page read on the first memory page utilizing a first trim value is performed responsive to initiating a memory page scan on a first memory page of a plurality of memory pages. Whether a first data state metric associated with the first page read satisfies a first threshold criterion is determined. A second page read on the first memory page utilizing a second trim value is performed responsive to determining that the first data state metric satisfies the first threshold criterion. Whether a second data state metric associated with the second page read satisfies a second threshold criterion is determined. The second trim value to perform subsequent page reads during memory page scans is selected responsive to determining that the second data state metric does not satisfy the first threshold criterion.

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