-
公开(公告)号:US10216495B2
公开(公告)日:2019-02-26
申请号:US15886390
申请日:2018-02-01
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor: Taylor L. Riche , Newton G. Petersen , Hojin Kee , Adam T. Arnesen , Haoran Yi , Dustyn K. Blasig , Tai A. Ly
IPC: G06F8/41
Abstract: System and method for convergence analysis. One or more state variables of a first program may be determined based on dependencies of variables in a first program. A second program corresponding to the first program is created based on the state variables and their dependencies, and executed multiple times. Each execution may include recording values of the state variables, determining an execution count, comparing the values to corresponding values from previous executions of the second program, and terminating the executing in response to the values matching corresponding values from at least one previous execution of the second program. A convergence property for the first program is determined based on the execution count, and indicating a number of executions of the first program required to generate all possible values of the one or more variables. The convergence property is stored, and may be useable to optimize the first program.
-
22.
公开(公告)号:US20180321925A1
公开(公告)日:2018-11-08
申请号:US15588298
申请日:2017-05-05
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor: Hojin Kee , David C. Uliana , Tai A. Ly , Adam T. Arnesen
IPC: G06F9/45
Abstract: System and method for compiling a program, including determining one or more program structures containing one or more variables at the entry and exit of each program structure, wherein each variable specifies a value transfer operation between outside the program structure and inside the program structure. Each value transfer operation may specify a value transfer between a respective one or more source variables and a destination variable. A subset of the destination variables may be determined for which assigning the destination variable to a memory resource of a corresponding source variable does not disrupt the functionality of the program. For each of the one or more value transfer operations, the value transfer operation may be implemented, where the implementation of the value transfer operation may be executable to assign each of the determined subset of destination variables to a respective memory resource, thereby mapping the variables to the memory resources, and dynamically change the mapping, including assigning the destination variable to the memory resource of a first source variable of the one or more source variables, thereby transferring the value from the first source variable to the destination variable without copying the value between the memory resources. The method may be implemented for programs operating according to either a static or dynamic schedule.
-
公开(公告)号:US20180181379A1
公开(公告)日:2018-06-28
申请号:US15886390
申请日:2018-02-01
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor: Taylor L. Riche , Newton G. Petersen , Hojin Kee , Adam T. Arnesen , Haoran Yi , Dustyn K. Blasig , Tai A. Ly
IPC: G06F8/41
Abstract: System and method for convergence analysis. One or more state variables of a first program may be determined based on dependencies of variables in a first program. A second program corresponding to the first program is created based on the state variables and their dependencies, and executed multiple times. Each execution may include recording values of the state variables, determining an execution count, comparing the values to corresponding values from previous executions of the second program, and terminating the executing in response to the values matching corresponding values from at least one previous execution of the second program. A convergence property for the first program is determined based on the execution count, and indicating a number of executions of the first program required to generate all possible values of the one or more variables. The convergence property is stored, and may be useable to optimize the first program.
-
公开(公告)号:US09990250B2
公开(公告)日:2018-06-05
申请号:US14725812
申请日:2015-05-29
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor: David C. Uliana , James W. McCoy , Newton G. Petersen , Tai A. Ly , Hojin Kee , Adam T. Arnesen
CPC classification number: G06F11/1008 , H03M13/1102 , H03M13/116 , H03M13/611 , H03M13/6502 , H03M13/6561
Abstract: Techniques are disclosed relating to implementation of LDPC encoding circuitry on a single integrated circuit (IC). In some embodiments, circuitry on a single IC includes message circuitry configured to receive or generate a message to be encoded, encode circuitry configured to perform low density parity check (LDPC) encoding on the message, noise circuitry configured to apply noise to the encoded message, and decode circuitry configured to perform LDPC decoding of the message. In some embodiments, the disclosed techniques may reduce production costs (e.g., by reducing overall chip area), facilitate LDPC testing, and/or provide multiple different functions relating to message transmission on a single chip.
-
公开(公告)号:US09740411B2
公开(公告)日:2017-08-22
申请号:US14523039
申请日:2014-10-24
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor: Tai A. Ly , Swapnil D. Mhaske , Hojin Kee , Adam T. Arnesen , David C. Uliana , Newton G. Petersen
CPC classification number: G06F3/0616 , G06F3/0604 , G06F3/0622 , G06F3/064 , G06F3/0659 , G06F3/0661 , G06F3/0673 , G06F11/1076 , G06F13/1615 , G06F13/1626 , G11C7/1039 , H03M13/1102 , H03M13/1105 , H03M13/114 , H03M13/6563 , H03M13/6566 , H03M13/6569 , Y02D10/14
Abstract: Techniques are disclosed relating to configuring an interlock memory system. In one embodiment, a method includes determining a sequence of memory access requests for a program and generating information specifying memory access constraints based on the sequence of memory accesses, where the information is usable to avoid memory access hazards for the sequence of memory accesses. In this embodiment, the method further includes configuring first circuitry using the information, where the first circuitry is included in or coupled to a memory. In this embodiment, after the configuring, the first circuitry is operable to perform memory access requests to the memory corresponding to the sequence of memory accesses while avoiding the memory access hazards, without receiving other information indicating the memory access hazards.
-
公开(公告)号:US09690550B2
公开(公告)日:2017-06-27
申请号:US14704689
申请日:2015-05-05
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor: Hojin Kee , Tai A. Ly , Newton G. Petersen , Jeffrey D. Washington , Haoran Yi , Dustyn K. Blasig
CPC classification number: G06F8/41 , G06F8/34 , G06F8/443 , G06F8/4435 , G06F8/447 , G06F8/48 , G06F8/49 , G06F11/3636
Abstract: When compiling high level, graphical code (e.g. LabVIEW™ code) representative of a design, parts of the code that do not depend on external input data may be executed during the compilation process. Specific variables and/or value traces of specific variables in the program, e.g. constant values and/or repeating patterns may be recorded then analyzed, and certain transformations may be applied in the compilation process according to the results of the analysis, thereby optimizing the design. In one approach, the graph may be dynamically stepped through one node at a time, and it may be determined whether all inputs to the stepped-through node are known. If those inputs are known, type conversion and the operation corresponding to the stepped-through node may be dynamically performed. In another approach, a subset of the graphical code not depending on external data may be compiled and executed, thereby obtaining the same results as described above.
-
公开(公告)号:US20170115885A1
公开(公告)日:2017-04-27
申请号:US15397107
申请日:2017-01-03
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor: Tai A. Ly , Swapnil D. Mhaske , Hojin Kee , Adam T. Arnesen , David C. Uliana , Newton G. Petersen
CPC classification number: G06F3/0616 , G06F3/0604 , G06F3/0622 , G06F3/064 , G06F3/0659 , G06F3/0661 , G06F3/0673 , G06F11/1076 , G06F13/1615 , G06F13/1626 , G11C7/1039 , H03M13/1102 , H03M13/1105 , H03M13/114 , H03M13/6563 , H03M13/6566 , H03M13/6569 , Y02D10/14
Abstract: Techniques are disclosed relating to self-addressing memory. In one embodiment, an apparatus includes a memory and addressing circuitry coupled to or comprised in the memory. In this embodiment, the addressing circuitry is configured to receive memory access requests corresponding to a specified sequence of memory accesses. In this embodiment, the memory access requests do not include address information. In this embodiment, the addressing circuitry is further configured to assign addresses to the memory access requests for the specified sequence of memory accesses. In some embodiments, the apparatus is configured to perform the memory access requests using the assigned addresses.
-
公开(公告)号:US09569119B2
公开(公告)日:2017-02-14
申请号:US14523413
申请日:2014-10-24
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor: Tai A. Ly , Swapnil D. Mhaske , Hojin Kee , Adam T. Arnesen , David C. Uliana , Newton G. Petersen
CPC classification number: G06F3/0616 , G06F3/0604 , G06F3/0622 , G06F3/064 , G06F3/0659 , G06F3/0661 , G06F3/0673 , G06F11/1076 , G06F13/1615 , G06F13/1626 , G11C7/1039 , H03M13/1102 , H03M13/1105 , H03M13/114 , H03M13/6563 , H03M13/6566 , H03M13/6569 , Y02D10/14
Abstract: Techniques are disclosed relating to self-addressing memory. In one embodiment, an apparatus includes a memory and addressing circuitry coupled to or comprised in the memory. In this embodiment, the addressing circuitry is configured to receive memory access requests corresponding to a specified sequence of memory accesses. In this embodiment, the memory access requests do not include address information. In this embodiment, the addressing circuitry is further configured to assign addresses to the memory access requests for the specified sequence of memory accesses. In some embodiments, the apparatus is configured to perform the memory access requests using the assigned addresses.
Abstract translation: 公开了涉及自寻址存储器的技术。 在一个实施例中,装置包括耦合到或包含在存储器中的存储器和寻址电路。 在该实施例中,寻址电路被配置为接收对应于指定的存储器访问序列的存储器访问请求。 在本实施例中,存储器访问请求不包括地址信息。 在该实施例中,寻址电路还被配置为为指定的存储器访问序列分配地址给存储器访问请求。 在一些实施例中,设备被配置为使用分配的地址来执行存储器访问请求。
-
公开(公告)号:US20160352458A1
公开(公告)日:2016-12-01
申请号:US14725914
申请日:2015-05-29
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor: David C. Uliana , Newton G. Petersen , Tai A. Ly , Hojin Kee , Adam T. Arnesen , Dustyn K. Blasig , Gandiinaa Gumenjav
CPC classification number: H03M13/1102 , H03M13/1137 , H03M13/118 , H03M13/611 , H03M13/616 , H03M13/6502 , H03M13/6561 , H04L1/0057
Abstract: Techniques are disclosed relating to encoding communications. In some embodiments, for different rows of an encoding matrix, the following operations are performed: generate a set of operations for entries in the row, where the set of operations includes respective operations to be performed on the entries for multiplication of the matrix by a vector, propagate values of entries in the encoding matrix into the set of operations, and simplify ones of the set of operations based on the propagated values to generate an output set of operations. In some embodiments, the output sets of operations are usable to encode input data for communication over a medium. In some embodiments, the disclosed techniques facilitate loop unrolling within compiler memory constraints. In some embodiments, an apparatus (e.g., a mobile device) is configured with the output sets of operations.
Abstract translation: 公开了与编码通信有关的技术。 在一些实施例中,对于编码矩阵的不同行,执行以下操作:为该行中的条目生成一组操作,其中该组操作包括要对矩阵乘以一个 向量,将编码矩阵中的条目的值传播到该组操作中,并且基于传播的值来简化该组操作中的一组,以生成输出操作集合。 在一些实施例中,输出操作组可用于编码用于通过介质进行通信的输入数据。 在一些实施例中,所公开的技术有助于循环在编译器存储器限制内展开。 在一些实施例中,设备(例如,移动设备)被配置有输出操作组。
-
30.
公开(公告)号:US20160352457A1
公开(公告)日:2016-12-01
申请号:US14725706
申请日:2015-05-29
Applicant: NATIONAL INSTRUMENTS CORPORATION
Inventor: David C. Uliana , Newton G. Petersen , Tai A. Ly , Qing Ruan , James C. Nagle , Swapnil D. Mhaske , Hojin Kee , Adam T. Arnesen
CPC classification number: H03M13/1102 , H03M13/611 , H03M13/6502 , H03M13/6561 , H04L1/0057
Abstract: Techniques are disclosed relating to LDPC encoding. In some embodiments, a set of operations is produced that is usable to generate an encoded message based on an input message. In some embodiments, the set of operations correspond to operations for entries in a smaller matrix representation that specifies locations of non-zero entries in an LDPC encoding matrix. In some embodiments, a mobile device is configured with the set of operations to perform LDPC encoding. Circuitry configured with the set of operations may perform LDPC encoding with high performance, relatively small area and/or low power consumption, in some embodiments.
Abstract translation: 公开了与LDPC编码相关的技术。 在一些实施例中,产生一组可用于基于输入消息生成编码消息的操作。 在一些实施例中,该组操作对应于在LDPC编码矩阵中指定非零条目的位置的较小矩阵表示中的条目的操作。 在一些实施例中,移动设备配置有用于执行LDPC编码的一组操作。 在一些实施例中,配置有该组操作的电路可以执行具有高性能,相对小的面积和/或低功耗的LDPC编码。
-
-
-
-
-
-
-
-
-