公开(公告)号：US20200057562A1

公开(公告)日：2020-02-20

申请号：US16450185

申请日：2019-06-24

Applicant: SK hynix Inc.

Inventor： Jong-Min LEE

IPC: G06F3/06 ,  G06F11/16 ,  G06F12/02

Abstract: A memory system includes a memory device including plural memory blocks storing a data, and a controller configured to divide a memory block into plural logical unit blocks, compare a valid page count of the memory block with a map data count of each logical unit block sequentially, and determine data validity of each logical unit block for a garbage collection operation based on a comparison result.

公开(公告)号：US20200042181A1

公开(公告)日：2020-02-06

申请号：US16408606

申请日：2019-05-10

Applicant: SK hynix Inc.

Inventor： Jong-Min LEE

IPC: G06F3/06 ,  G06F12/02

Abstract: A memory system includes a non-volatile memory device including plural memory blocks storing a data; and a controller suitable for increasing a count of blocks to be erasable among the plural memory blocks. The controller can repeatedly search for valid data in a predetermined range of the plural memory blocks during an idle state.

公开(公告)号：US20200034081A1

公开(公告)日：2020-01-30

申请号：US16295635

申请日：2019-03-07

Applicant: SK hynix Inc.

Inventor： Jong-Min LEE

IPC: G06F3/06

Abstract: A memory system includes a memory device and a controller. The memory device includes plural blocks, each capable of storing data. The controller records operation information used for determining which blocks among the plural blocks a voluminous data is to be programmed. The voluminous data has a size that requires at least two blocks among the plural blocks. After performing a program operation of the voluminous data, the controller can resume the program operation based on the operation information after the program operation is halted.

公开(公告)号：US20190258577A1

公开(公告)日：2019-08-22

申请号：US16123467

申请日：2018-09-06

Applicant: SK hynix Inc.

Inventor： Jong-Min LEE ,  Beom-Rae JEONG

IPC: G06F12/0868 ,  G06F12/0831 ,  G06F3/06

Abstract: A memory system may include: a nonvolatile memory device comprising a plurality of memory blocks each of which includes a plurality of pages; a volatile memory device configured to temporarily store data to be transmitted between a host and the nonvolatile memory device; and a controller configured to enter an exclusive mode in response to a request of the host, a result of checking a state of the nonvolatile memory device, or performing a merge operation on the nonvolatile memory device, exclusively use the volatile memory device to perform the merge operation during an entry period of the exclusive mode, and exit the exclusive mode in response to completing the performing of the merge operation.

公开(公告)号：US20190236005A1

公开(公告)日：2019-08-01

申请号：US16109070

申请日：2018-08-22

Applicant: SK hynix Inc.

Inventor： Jong-Min LEE

IPC: G06F12/02 ,  G06F3/06 ,  G06F11/14 ,  G06F11/10

CPC classification number: G06F12/0253 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0689 ,  G06F11/108 ,  G06F11/1441 ,  G06F2212/262 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7208

Abstract: A memory system includes a memory device, and a controller suitable for selecting at least one common operation necessary to be performed in first and second tasks, selecting the first or second task, and selectively performing one or more of a valid data scan operation, a valid data read operation, a valid data write operation, and a valid data map update operation based on selected information, wherein the first task is a garbage collection operation performed on a host data block, a system data block and a map data block, wherein the second task is a recovery operation performed after a sudden power-off (SPO) that occurs during the valid data map update operation.

公开(公告)号：US20190198116A1

公开(公告)日：2019-06-27

申请号：US16037661

申请日：2018-07-17

Applicant: SK hynix Inc.

Inventor： Jong-Min LEE

IPC: G11C16/10 ,  G11C16/04

Abstract: A semiconductor memory system includes a memory device including a plurality of memory blocks; a partial memory block detector suitable for detecting at least one partial memory block among the plurality of memory blocks; an open page detector suitable for detecting addresses and a number of a plurality of open pages among a plurality of pages included in the partial memory block; and a controller suitable for controlling the memory device to perform a one-shot program operation with dummy data according to the addresses and the number of the plurality of open pages.

公开(公告)号：US20190179548A1

公开(公告)日：2019-06-13

申请号：US16041298

申请日：2018-07-20

Applicant: SK hynix Inc.

Inventor： Jong-Min LEE

IPC: G06F3/06

Abstract: A memory system may include: a memory device including a plurality of pages in which data are stored and a plurality of memory blocks in which the pages are included; and a controller suitable for performing command operations corresponding to a plurality of commands received from a host, in the memory blocks, checking parameters for the memory blocks corresponding to performing the command operations, and allocating second memory blocks as first target memory blocks based on the parameters after skipping the first memory blocks among the memory blocks.

公开(公告)号：US20180024770A1

公开(公告)日：2018-01-25

申请号：US15438890

申请日：2017-02-22

Applicant: SK hynix Inc.

Inventor： Jong-Min LEE

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7207

Abstract: A memory system may include: a memory device including memory blocks each memory block including pages, each page including memory cells which are coupled to a word line for storing data; and a controller including a memory, the controller receiving a write command and a read command from a host, storing write data corresponding to the write command in the memory, transmitting and storing the write data stored in the memory to and in at least one first memory device buffer coupled to a first memory block in a page of which the write data are to be stored, reading read data corresponding to the read command from a page of a second memory block, storing the read data in at least one second memory device buffer coupled to the second memory block, and storing the read data stored in the second memory device buffer, in the memory.

公开(公告)号：US20170220472A1

公开(公告)日：2017-08-03

申请号：US15204401

申请日：2016-07-07

Applicant: SK hynix Inc.

Inventor： Byoung-Sung YOU ,  Jin-Woong KIM ,  Jong-Min LEE

IPC: G06F12/0868 ,  G06F12/0804

CPC classification number: G06F12/0868 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0804 ,  G06F2212/1021 ,  G06F2212/2022 ,  G06F2212/281 ,  G06F2212/312 ,  G06F2212/608 ,  G06F2212/7203

Abstract: A memory system may include a plurality of first and second memory devices each comprising M-bit multi-level cells (MLCs), M-bit multi-buffers, and transmission buffers, a cache memory suitable for caching data inputted to or outputted from the plurality of first and second memory devices, and a controller suitable for programming program data cached by the cache memory to a memory device selected among the first and second memory devices by transferring the program data to M-bit multi-buffers of the selected memory device whenever the program data are cached by M bits into the cache memory, and controlling the selected memory device to perform a necessary preparation operation, except for a secondary preparation operation, of a program preparation operation, until an input of the program data is ended or the M-bit multi-buffers of the selected memory device are full.

公开(公告)号：US20170139646A1

公开(公告)日：2017-05-18

申请号：US15096160

申请日：2016-04-11

Applicant: SK hynix Inc.

Inventor： Jong-Min LEE

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/08

CPC classification number: G06F3/0659 ,  G06F3/0608 ,  G06F3/0626 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/1018 ,  G06F2212/1016 ,  G06F2212/60 ,  G06F2212/7201

Abstract: A memory system may include a memory device comprising a plurality of memory blocks each having a plurality of pages; and a controller suitable for storing data in a first memory block among the memory blocks, storing map data of the data in a second memory block among the memory blocks, and scanning the map data by performing filtering on logical information of the data in response to a command.