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    ULTRA-LOW-POWER SPEECH FEATURE EXTRACTION CIRCUIT BASED ON NON-OVERLAPPING FRAMING AND SERIAL FFT
    22.
    发明申请
    ULTRA-LOW-POWER SPEECH FEATURE EXTRACTION CIRCUIT BASED ON NON-OVERLAPPING FRAMING AND SERIAL FFT 有权

    公开(公告)号：US20220189459A1

    公开(公告)日：2022-06-16

    申请号：US17181908

    申请日：2021-02-22

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weiwei SHAN ,  Lixuan ZHU ,  Jun YANG ,  Longxing SHI

    IPC: G10L15/02 ,  G10L25/24 ,  G06F17/14

    Abstract: The present invention discloses an ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial fast Fourier transform (FFT), and belongs to the technical field of computation, calculation or counting. The circuit is oriented to the field of intelligence, and is integrally composed of a pre-process module, a windowing module, a Fourier transform module, a Mel filtering module, an adjacent frame merging module, a discrete cosine transform (DCT) module and other modules by optimizing the architecture of a Mel-frequency Cepstral Coefficients (MFCC) algorithm. Large-scale storage caused by framing is avoided in a non-overlapping framing mode, storage contained in the MFCC algorithm is further reduced, and the circuit area and the power consumption are greatly reduced. An FFT algorithm in the feature extraction circuit adopts a serial pipeline mode to process data, makes full use of the characteristics of serial inflow of audio data, and further reduces the storage area and operations of the circuit.

    GRAPHENE CHANNEL SILICON CARBIDE POWER SEMICONDUCTOR TRANSISTOR
    23.
    发明申请
    GRAPHENE CHANNEL SILICON CARBIDE POWER SEMICONDUCTOR TRANSISTOR 有权

    公开(公告)号：US20210336009A1

    公开(公告)日：2021-10-28

    申请号：US16486494

    申请日：2018-09-25

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weifeng SUN ,  Siyang LIU ,  Lizhi TANG ,  Sheng LI ,  Chi ZHANG ,  Jiaxing WEI ,  Shengli LU ,  Longxing SHI

    IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78

    Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.

    BI-DIRECTIONAL ADAPTIVE CLOCKING CIRCUIT SUPPORTING A WIDE FREQUENCY RANGE
    24.
    发明申请
    BI-DIRECTIONAL ADAPTIVE CLOCKING CIRCUIT SUPPORTING A WIDE FREQUENCY RANGE 有权

    公开(公告)号：US20210313975A1

    公开(公告)日：2021-10-07

    申请号：US16957724

    申请日：2019-07-09

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weiwei SHAN ,  Jun YANG ,  Longxing SHI

    IPC: H03K5/14 ,  H03K5/131 ,  G04F10/00

    Abstract: A two-way adaptive clock circuit supporting a wide frequency range is composed of a phase clock generating module, a phase clock selecting module, an adaptive clock stretching or compressing amount regulating circuit module and a control module. The adaptive clock stretching or compressing amount regulating circuit module can monitor delay information of a critical path in a chip in real time and feed the information back into the control module. After receiving a clock stretching or compressing enable signal and a stretching or compressing scale signal, the control module selects a target phase clock from clocks generated by the phase clock generating module to rapidly regulate an adaptive clock in a current cycle. The present invention is applied to an adaptive voltage frequency regulating circuit based on on-line time sequence monitoring.

    ULTRA-LOW POWER KEYWORD SPOTTING NEURAL NETWORK CIRCUIT
    25.
    发明申请
    ULTRA-LOW POWER KEYWORD SPOTTING NEURAL NETWORK CIRCUIT 有权

    公开(公告)号：US20210089874A1

    公开(公告)日：2021-03-25

    申请号：US17112329

    申请日：2020-12-04

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weiwei SHAN ,  Boyang CHENG ,  Jun YANG ,  Longxing SHI

    IPC: G06N3/063 ,  G06N3/04 ,  G06F1/3203

    Abstract: It discloses an ultra-low power keyword spotting neural network circuit and a method for mapping data. A neural network model used is a depthwise separable convolutional neural network, of which a weight value and an intermediate activation value are both binarized during training, to obtain a lightweight neural network model with a small memory size and a small computation quantity. The circuit is designed on the basis of a data processing unit array, utilizes a memory module to memorize a weight parameter and intermediate data of a keyword spotting neural network, data control and accuracy configuration of the data processing unit array are completed by means of a control module and a data mapping module, and the data processing unit array performs a neural network computation with hybrid accuracy; and the method for mapping the data configures.

    A PVTM-based Wide Voltage Range Clock Stretching Circuit
    26.
    发明申请
    A PVTM-based Wide Voltage Range Clock Stretching Circuit 审中-公开

    公开(公告)号：US20180191335A1

    公开(公告)日：2018-07-05

    申请号：US15562893

    申请日：2017-02-24

    Applicant: Southeast University

    Inventor： Weiwei SHAN ,  Liang WAN ,  Longxing SHI

    IPC: H03K5/133 ,  H03L7/18

    CPC classification number: H03K5/133 ,  H03K5/05 ,  H03L7/18

    Abstract: A PVTM-based wide voltage range clock stretching circuit is disclosed. The circuit consists of a PVTM circuit module, a phase clock generation module, a clock synchronization selection module and a control module. The PVTM circuit module monitors in real time the delay information of an on-chip delay unit to monitor the operating environment of the circuit, and feeds the delay information back to the control module. Under the control of a clock stretching enable signal and a clock stretching extent signal, the control module selects a target phase clock from the clocks generated by the phase clock generation module in accordance with the feedback from the PVTM, enabling the stretching of system clock within a single cycle in different PVT conditions. Sophisticated gate devices are not required, and the cost of area and power consumption are kept to minimal.

    ERROR RECOVERY CIRCUIT FACING CPU ASSEMBLY LINE
    27.
    发明申请
    ERROR RECOVERY CIRCUIT FACING CPU ASSEMBLY LINE 有权
    CPU组装线上出现故障恢复电路

    公开(公告)号：US20150309897A1

    公开(公告)日：2015-10-29

    申请号：US14442071

    申请日：2013-08-30

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weiwei SHAN ,  Chaoxuan TIAN ,  Huafang SUN ,  Longxing SHI

    IPC: G06F11/20

    CPC classification number: G06F11/2035 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/1402 ,  G06F11/3024 ,  G06F11/3062 ,  G06F11/3093 ,  G06F2201/805 ,  G06F2201/85 ,  Y02D10/126 ,  Y02D10/172

    Abstract: Disclosed is an error recovery circuit facing a CPU assembly line, comprising: on-chip monitoring circuits (1), an error signal statistics module (2), a voltage frequency control module (3), an error recovery control module (4), an in-situ error recovery module (5) and an upper-layer error recovery module (6), wherein each of the on-chip monitoring circuits (1) is integrated at the end of each stage of assembly lines of the previous N−1 stages of assembly lines of a CPU kernel with an N-stage assembly line structure, so as to monitor the time sequence information about each clock period of an operating circuit, wherein N is a positive integer which is greater than or equal to 3 and less than 20. The present invention provides the on-line time sequence monitoring on the CPU kernel with N stages of assembly lines to search for the lowest possible operating voltage of the circuit, and to reduce the margin of the operating voltage reserved for the circuit in the design stage, thereby significantly reducing the power consumption of the circuit and improving the energy efficiency of the circuit.

    Abstract translation: 公开了面向CPU装配线的错误恢复电路，包括：片上监控电路（1），误差信号统计模块（2），电压频率控制模块（3），错误恢复控制模块（4） 原位错误恢复模块（5）和上层错误恢复模块（6），其中片上监控电路（1）中的每一个在前一个N- 1级具有N级组装线结构的CPU内核的组装线，以便监视关于操作电路的每个时钟周期的时间序列信息，其中N是大于或等于3的正整数，以及 小于20.本发明提供了在具有N级装配线的CPU内核上的在线时间序列监视，以搜索电路的最低可能工作电压，并且减小为电路保留的工作电压的余量 在设计阶段，从而得到信誉 显着降低电路的功耗并提高电路的能量效率。

    MULTI-PHASE HIGH-PRECISION CURRENT SHARING CONTROL METHOD APPLIED TO CONSTANT ON-TIME CONTROL
    29.
    发明公开
    MULTI-PHASE HIGH-PRECISION CURRENT SHARING CONTROL METHOD APPLIED TO CONSTANT ON-TIME CONTROL 审中-公开

    公开(公告)号：US20240266943A1

    公开(公告)日：2024-08-08

    申请号：US18641384

    申请日：2024-04-21

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Shen XU ,  Haiqing ZHANG ,  Yujie LIU ,  Ruizhi WANG ,  Yuan GAO ,  Yongjia LI ,  Weifeng SUN ,  Longxing SHI

    IPC: H02M1/08 ,  H02M1/00 ,  H02M3/158

    CPC classification number: H02M1/082 ,  H02M1/0025 ,  H02M3/1586

    Abstract: A multi-phase high-precision current sharing control method applied to constant on-time control is provided, wherein a current difference between continuously sampled current of each line and mean current is processed by a PI compensation module and a low-pass filter module to obtain on-time regulation data. A high bit of the regulation data controls the value of counter reference Vref in an on-time control module, and a low bit controls the length of an enabled delay line in a delay line module. The counter timing control of the on-time control module is combined with the delay line timing control of the delay line module to improve the control precision of a DPWM. The method takes COT control of a Buck converter as a typical application. Compared with a multi-phase COT controller without a current-sharing mechanism, the method can improve the stability and reliability of the system.

    HIGH-THRESHOLD POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    30.
    发明申请
    HIGH-THRESHOLD POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220367716A1

    公开(公告)日：2022-11-17

    申请号：US17762929

    申请日：2021-01-20

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Siyang LIU ,  Weifeng SUN ,  Chi ZHANG ,  Shuxuan XIN ,  Shen LI ,  Le QIAN ,  Chen GE ,  Longxing SHI

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/812 ,  H01L29/778

    Abstract: The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the metal gate electrode and the source metal electrode only exist in the cell region, and the passivation layer of the terminal region extends upwards and is wrapped outside the channel layer. This structure can increase a threshold voltage of the device, improve the blocking characteristics of the device and reduce the size of a gate capacitance.

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