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    Linear regulation of SPAD shutoff voltage
    21.
    发明授权
    Linear regulation of SPAD shutoff voltage 有权

    公开(公告)号：US11530947B1

    公开(公告)日：2022-12-20

    申请号：US17370230

    申请日：2021-07-08

    Applicant: STMicroelectronics (Research & Development) Limited

    Inventor： John Kevin Moore

    IPC: G01J1/44

    Abstract: Described herein is an electronic device, including a pixel and a turn-off circuit. The pixel includes a single photon avalanche diode (SPAD) having a cathode coupled to a high voltage node and an anode selectively coupled to ground through an enable circuit, and a clamp diode having an anode coupled to the anode of the SPAD and a cathode coupled to a turn-off voltage node. The turn-off circuit includes a sense circuit coupled between the turn-off voltage node and ground and configured to generate a feedback voltage, and a regulation circuit configured to sink current from the turn-off voltage node to ground based upon the feedback voltage such that a voltage at the turn-off voltage node maintains generally constant.

    Proximity sensor and method of operating a photodetector based proximity sensor
    22.
    发明授权
    Proximity sensor and method of operating a photodetector based proximity sensor 有权

    公开(公告)号：US11146270B2

    公开(公告)日：2021-10-12

    申请号：US16535369

    申请日：2019-08-08

    Applicant: STMicroelectronics (Research & Development) Limited

    Inventor： John Kevin Moore

    IPC: H03K17/94 ,  H01L31/0232 ,  H01L31/12 ,  H03K17/945

    Abstract: An apparatus can be used for detecting pile-up within circuitry associated with photodetectors. The apparatus includes an input terminal configured to receive a plurality of photodetector outputs. An OR-tree is coupled in parallel with the circuitry associated with the photodetectors. The OR-tree has an input coupled to the input terminal and is configured to combine the photodetector outputs. A counter is configured to count an output of the OR-tree. A comparator is configured to compare an output of the counter to a determined threshold value, wherein the comparator is configured to output an indicator indicating pile-up within the circuitry associated with photodetectors based on the output of the counter being greater than or equal to the determined threshold value.

    Single Reference Clock Time to Digital Converter
    25.
    发明申请
    Single Reference Clock Time to Digital Converter 审中-公开

    公开(公告)号：US20190230304A1

    公开(公告)日：2019-07-25

    申请号：US15877551

    申请日：2018-01-23

    Applicant: STMicroelectronics (Research & Development) Limited

    Inventor： John Kevin Moore ,  Neale Dutton

    IPC: H04N5/376 ,  G04F10/00 ,  H03M1/12 ,  H04N5/3745 ,  H04N5/378

    Abstract: In an embodiment, a TDC includes: a clock input configured to receive a reference clock that is synchronized with a first event; a clock generation circuit configured to generate a first clock at a first output of the clock generation circuit based on the reference clock, the first clock having a second frequency lower than the reference clock; a data input configured to receive an input stream of pulses, where the input stream of pulses is based on the first event; a sampling circuit having an input register, the sampling circuit coupled to the data input, the sampling circuit configured to continuously sample the input stream of pulses into the input register based on the reference clock; and output terminals configured to stream time stamps based on the input stream of pulses at the second frequency, where the stream of time stamps is synchronized with the first clock.

    Time to digital converter (TDC) with synchronous output and related methods
    26.
    发明授权
    Time to digital converter (TDC) with synchronous output and related methods 有权

    公开(公告)号：US10067224B2

    公开(公告)日：2018-09-04

    申请号：US14920344

    申请日：2015-10-22

    Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED

    Inventor： John Kevin Moore ,  Neale Dutton

    IPC: G01S7/48 ,  G01S7/486 ,  G04F10/00

    Abstract: A time to digital converter (TDC) may include a sampling stage configured to sample an input signal based upon a plurality of timing signals having different respective phases, and provide a respective output for each of the different timing signals. A first synchronization stage may be configured to receive the outputs from the sampling stage, synchronize a first subset of the outputs to a first one of the plurality of timing signals, and synchronize a second subset of the outputs to a second one of the plurality of timing signals. A second synchronization stage may be configured to receive the synchronized outputs from the first synchronization stage, and synchronize all of the synchronized outputs from the first synchronization stage to the first one of the plurality of timing signals.

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