公开(公告)号：US10453911B2

公开(公告)日：2019-10-22

申请号：US15965160

申请日：2018-04-27

Applicant: Samsung Display Co., Ltd.

Inventor： Myoung Geun Cha ,  Sang Gun Choi ,  Thanh Tien Nguyen ,  Kyoung Won Lee ,  Yong Su Lee ,  Joo Hye Jung

IPC: H01L27/32 ,  G09G3/3233 ,  G09G3/3258

Abstract: A display device includes first semiconductor pattern including a first channel portion, a first electrode connected to a driving voltage line, and a second electrode connected to a light emitting element, a first insulating, a first conductive layer including a first gate electrode, a second insulating layer, a second conductive layer including an initialization power line, a third insulating layer, an upper semiconductor layer including a second semiconductor pattern including a second channel portion, a third electrode, and a fourth electrode connected to the first gate electrode, and a third semiconductor pattern including a third channel portion, a fifth electrode connected to the third electrode, and a sixth electrode connected to the second electrode, a fourth insulating layer, and a third conductive layer including a scan line and a control signal line, wherein the upper semiconductor layer does not overlap the first gate electrode and the initialization power line.

公开(公告)号：US09768309B2

公开(公告)日：2017-09-19

申请号：US15194841

申请日：2016-06-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang ,  Dae Ho Kim ,  Jae Neung Kim ,  Myoung Geun Cha ,  Sang Gab Kim ,  Yu-Gwang Jeong

IPC: H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/417 ,  H01L27/32

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

公开(公告)号：US09368515B2

公开(公告)日：2016-06-14

申请号：US14070886

申请日：2013-11-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Dong Jo Kim ,  Ji Seon Lee ,  Jong Chan Lee ,  Yoon Ho Khang ,  Sang Ho Park ,  Yong Su Lee ,  Jung Kyu Lee

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288

Abstract: A thin film transistor array panel may include a channel layer including an oxide semiconductor and formed in a semiconductor layer, a source electrode formed in the semiconductor layer and connected to the channel layer at a first side, a drain electrode formed in the semiconductor layer and connected to the channel layer at an opposing second side, a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode, an insulating layer disposed on the channel layer, a gate line including a gate electrode disposed on the insulating layer, a passivation layer disposed on the source and drain electrodes, the pixel electrode, and the gate line, and a data line disposed on the passivation layer. A width of the channel layer may be substantially equal to a width of the pixel electrode in a direction parallel to the gate line.

Abstract translation: 薄膜晶体管阵列面板可以包括在半导体层中形成的氧化物半导体的沟道层，形成在半导体层中并连接到第一侧的沟道层的源电极，形成在半导体层中的漏电极和 连接到相对的第二侧的沟道层，形成在与漏电极的半导体层相同的部分中的半导体层中的像素电极，设置在沟道层上的绝缘层，设置在栅电极上的栅极线 绝缘层，设置在源电极和漏电极上的钝化层，像素电极和栅极线以及设置在钝化层上的数据线。 沟道层的宽度可以基本上等于像素电极在与栅极线平行的方向上的宽度。

公开(公告)号：US09034691B2

公开(公告)日：2015-05-19

申请号：US14468472

申请日：2014-08-26

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang

IPC: H01L21/02 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L21/385 ,  H01L21/441

CPC classification number: H01L29/7869 ,  H01L21/0262 ,  H01L21/385 ,  H01L21/441 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78633 ,  H01L29/78696

Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract translation: 提供一种薄膜晶体管，包括该薄膜晶体管的薄膜晶体管阵列面板及其制造方法，其中薄膜晶体管包括沟道区，该沟道区包括氧化物半导体，源极区和连接到沟道的漏极区 区域，并且相对于沟道区域在两侧面对，位于沟道区域上的绝缘层和位于绝缘层上的栅电极，其中栅电极的边缘边界和沟道区域的边缘边界 基本对齐。

公开(公告)号：US20140167040A1

公开(公告)日：2014-06-19

申请号：US14184361

申请日：2014-02-19

Applicant: Samsung Display Co., Ltd.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang ,  Dae Ho Kim ,  Jae Neung Kim ,  Myoung Geun Cha ,  Sang Gab Kim ,  Yu-Gwang Jeong

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管包括氧化物半导体。 源电极和漏电极彼此面对。 源电极和漏电极分别位于氧化物半导体的两个相对侧。 低导电区域位于源电极或漏电极与氧化物半导体之间。 绝缘层位于氧化物半导体和低导电区域上。 栅电极位于绝缘层上。 绝缘层覆盖氧化物半导体和低导电区域。 低导电区域的载流子浓度低于源电极或漏电极的载流子浓度。

公开(公告)号：US12302717B2

公开(公告)日：2025-05-13

申请号：US16857888

申请日：2020-04-24

Applicant: Samsung Display Co., LTD.

Inventor： Keun Woo Kim ,  Sang Sub Kim ,  Hye Na Kwak ,  Doo Na Kim ,  Thanh Tien Nguyen ,  Yong Su Lee ,  Jae Hwan Chu

IPC: H10K59/131 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3291

Abstract: A display device includes pixels at least one of which includes a light emitting element connected between a first power source and a second power source, a first transistor connected between the first power source and the light emitting element and controlling a driving current flowing through the light emitting element in response to a voltage of a first node, a switching transistor connected to the first node and including and active layer that includes first and second conductive regions spaced apart from each other, first and second channel regions disposed between the first and second conductive regions, and a common conductive region disposed between the first and second channel regions, and a conductive pattern overlapping the active layer to face the common conductive region.

公开(公告)号：US11910664B2

公开(公告)日：2024-02-20

申请号：US17252670

申请日：2018-12-18

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Myoung Geun Cha ,  Sang Gun Choi ,  Ji Yeong Shin ,  Yong Su Lee

IPC: H10K59/131 ,  G09G3/32 ,  H10K59/123 ,  H10K77/10 ,  H10K102/00

CPC classification number: H10K59/131 ,  G09G3/32 ,  H10K59/123 ,  H10K77/111 ,  G09G2300/0426 ,  G09G2300/0809 ,  G09G2320/02 ,  H10K2102/311

Abstract: A display device includes a substrate including a display area including a plurality of pixels, a peripheral area around the display area, and a bending area disposed in the peripheral area. A plurality of transistors is disposed in each pixel; a driving voltage line is disposed in the display area and transmits a driving voltage; a driving voltage transmission line is disposed in the peripheral area and is connected to the driving voltage line; and a conductive overlap layer overlaps at least one of the plurality of transistors.

公开(公告)号：US11594639B2

公开(公告)日：2023-02-28

申请号：US17115470

申请日：2020-12-08

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang ,  Dae Ho Kim ,  Jae Neung Kim ,  Myoung Geun Cha ,  Sang Gap Kim ,  Yu-Gwang Jeong

IPC: H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/417 ,  H01L27/32

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

公开(公告)号：US11502282B2

公开(公告)日：2022-11-15

申请号：US17075872

申请日：2020-10-21

Applicant: Samsung Display Co., Ltd.

Inventor： Myoung Geun Cha ,  Sang Gun Choi ,  Joon Woo Bae ,  Ji Yeong Shin ,  Yong Su Lee

IPC: H01L51/56 ,  H01L27/32 ,  H01L21/308 ,  H01L51/52

Abstract: A display device includes a first transistor including a first active layer, a first gate electrode overlapping the first active layer, a gate insulating layer between the first active layer and the first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second active layer, a second gate electrode overlapping the second active layer, a second source electrode and a second drain electrode; a capacitor including a first capacitor electrode connected to the second transistor; a lower electrode disposed under the first active layer; a connecting member connecting the first active layer to the lower electrode; and a first metal pattern contacting the connecting member and disposed on a same layer with the first gate electrode.

公开(公告)号：US11450722B2

公开(公告)日：2022-09-20

申请号：US16871523

申请日：2020-05-11

Applicant: Samsung Display Co., Ltd.

Inventor： Doo Na Kim ,  Keun Woo Kim ,  Tae Wook Kang ,  Do Kyeong Lee ,  Yong Su Lee ,  Jae Hwan Chu ,  Kwang Hyun Kim ,  Yeoung Keol Woo ,  Yung Bin Chung

IPC: H01L27/14 ,  H01L27/32 ,  H01L29/786 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

Abstract: A display device includes: a first semiconductor layer on a first buffer layer, and including a first active layer; a first gate insulating layer on the first semiconductor layer, and covering the first active layer; a first conductive layer on the first gate insulating layer, and including a first gate electrode; a second conductive layer on the first conductive layer, and including a first source/drain electrode; a first interlayer insulating layer on the first conductive layer; a second semiconductor layer on the first interlayer insulating layer, and including a second active layer; a second gate insulating layer on the second semiconductor layer, and covering the second active layer; and a third conductive layer on the second gate insulating layer, and including a second gate electrode and a second source/drain electrode. The first gate insulating layer and the second gate insulating layer include different insulating materials from each other.