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    SEMICONDUCTOR MEMORY DEVICE INCLUDING PARALLEL STRUCTURE
    21.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING PARALLEL STRUCTURE 审中-公开

    公开(公告)号：US20200312379A1

    公开(公告)日：2020-10-01

    申请号：US16591061

    申请日：2019-10-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Bongsoon Lim ,  Hojoon Kim ,  Sang-won Park ,  Sang-won Shim ,  Wonbo Shim

    IPC: G11C5/02 ,  G11C8/08 ,  G11C8/06 ,  G11C8/18 ,  G11C5/06 ,  G11C7/18 ,  G11C8/14

    Abstract: A semiconductor memory device includes a substrate, first memory cells that are connected to first word lines extending along a first direction and first bit lines extending along a second direction, over the substrate, first conductive materials that are connected to the first word lines and extend from the first word lines along a third direction perpendicular to the first direction and the second direction, second conductive materials that are connected to the first bit lines and extend along the first direction over the first bit lines, and third conductive materials that are connected to the second conductive materials and extend from the second conductive materials along the third direction.

    Non-volatile memory device
    22.
    发明授权
    Non-volatile memory device 有权

    公开(公告)号：US12131784B2

    公开(公告)日：2024-10-29

    申请号：US17742874

    申请日：2022-05-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangwon Park ,  Bongsoon Lim ,  Byungsoo Kim

    IPC: G11C16/00 ,  G11C5/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30

    CPC classification number: G11C16/16 ,  G11C5/063 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30

    Abstract: A non-volatile memory device includes a plurality of word lines stacked above a substrate in a vertical direction; erase control lines that are spaced apart from each other in a first direction and extend in a second direction; a pass transistor circuit including a first pass transistor connected to a first group of erase control lines and a second pass transistor connected to a second group of erase control lines; and a memory cell array including a plurality of blocks. The first group of erase control lines are relatively close to a word line cut region and the second group of erase control lines are relatively far from the word line cut region. Each of the plurality of blocks includes a plurality of channel structures connected to the word lines and the erase control lines and each channel structure extends in the vertical direction.

    MEMORY DEVICES
    24.
    发明申请
    MEMORY DEVICES 有权

    公开(公告)号：US20230123297A1

    公开(公告)日：2023-04-20

    申请号：US17863697

    申请日：2022-07-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byungsoo Kim ,  Sangwan Nam ,  MinJae Seo ,  Bongsoon Lim

    IPC: H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A memory device includes a first cell array region and a second cell array region separated by a separation region, each including at least one memory block having a plurality of gate electrode layers stacked in a first direction. The gate electrode layers include an upper select electrode layer including a plurality of string select lines, and a first electrode layer including a plurality of first word lines arranged below the string select lines. The first word lines include a first connection line to connect first end portions of the first word lines positioned on the opposite side of the separation region to each other and a plurality of second connection lines to connect some of second end portions of the plurality of first word lines adjacent to the separation region to each other, wherein each of the second connection lines is shorter than the first connection line.

    Memory device having different numbers of bits stored in memory cells
    25.
    发明授权
    Memory device having different numbers of bits stored in memory cells 有权

    公开(公告)号：US11024363B2

    公开(公告)日：2021-06-01

    申请号：US16810527

    申请日：2020-03-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yonghyuk Choi ,  Bongsoon Lim ,  Jaeduk Yu

    IPC: G11C5/02 ,  G11C11/408 ,  G11C11/4094 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04

    Abstract: A memory device includes word lines stacked on an upper surface of a substrate, channel structures penetrating through the word lines, and each including channel regions connected to one another in a first direction perpendicular to the upper surface of the substrate, and word-line cuts extending in the first direction and dividing the word lines to blocks. The word lines and the channel structures provide memory cell strings, and each of the memory cell strings include memory cells arranged in the first direction. The memory cells included in at least one of the memory cell strings include a first memory cell and a second memory cell disposed at different positions in the first direction, and the number of bits of data stored in the first memory cell is less than the number of bits of data stored in the second memory cell.

    NONVOLATILE MEMORY DEVICE WITH ADDRESS RE-MAPPING
    27.
    发明申请
    NONVOLATILE MEMORY DEVICE WITH ADDRESS RE-MAPPING 有权

    公开(公告)号：US20210098072A1

    公开(公告)日：2021-04-01

    申请号：US17022967

    申请日：2020-09-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

    IPC: G11C29/00 ,  G11C7/10 ,  G11C29/18 ,  G11C29/44 ,  G11C29/12

    Abstract: A nonvolatile memory device includes memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, is connected to the memory cell region by the first metal pad and the second metal pad and includes including an address decoder and a page buffer circuit located on a first substrate. A memory cell array is provided in the memory cell region, which includes a first vertical structure on a second substrate. The first vertical structure includes first sub-blocks and first via areas in which one or more through-hole vias are provided, and through-hole vias pass through the first vertical structure. A control circuit in the peripheral circuit region groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

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