公开(公告)号：US20250133738A1

公开(公告)日：2025-04-24

申请号：US18661467

申请日：2024-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chulmin Choi ,  Changhee Lee ,  Dajin Kim ,  Jiwoong Kim ,  Tae Hun Kim ,  Sang-Yong Park ,  Seung Jae Baik ,  Gun-Wook Yoon ,  Jaeduk Lee

IPC: H10B43/27 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a gate stack with alternating conductive patterns and insulating patterns. The device also includes a first memory channel structure including a first channel layer enclosed by the gate stack and a first memory layer enclosing the first channel layer. The device also includes a source structure electrically connected to the first channel layer. The source structure includes several source layers stacked atop one another. The first channel layer is in physical contact with the second source layer but apart from the other source layers. The first source layer contains impurities of a first conductivity type. The second source layer is formed of an impurity-free material. The third source layer contains impurities of a second conductivity type different from the first conductivity type.

公开(公告)号：US20250048627A1

公开(公告)日：2025-02-06

申请号：US18427977

申请日：2024-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeok Heo ,  Kyoung-Ho Kim ,  Hojun Lee ,  Sungsu Moon ,  Sea Hoon Lee ,  Jaeduk Lee ,  Junhee Lim

IPC: H10B43/27 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: Disclosed are semiconductor devices and electronic systems including the same. The semiconductor device includes a substrate that has a recess region, a gate electrode on a bottom surface of the recess region, a gate dielectric layer between the gate electrode and the bottom surface of the recess region, a plurality of shield electrodes on laterally opposite sides of the gate electrode and on inner sidewalls of the recess region, a plurality of dielectric patterns between the shield electrodes and the inner sidewalls of the recess region, a plurality of impurity regions in the substrate and on opposite sides of the shield electrodes, and a channel region in the substrate and below the bottom surface of the recess region.

公开(公告)号：US11966625B2

公开(公告)日：2024-04-23

申请号：US17722850

申请日：2022-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Guyeon Han ,  Sangwon Park ,  Jinkyu Kang ,  Raeyoung Lee ,  Jaeduk Lee

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Provided are a memory device storing setting data and a memory system including the same. The memory device may include a cell array including a plurality of cell blocks, each including a plurality of pages, and a control logic that controls a program and read operation on the cell array, wherein at least one page of the cell array stores information data read (IDR) data including information related to a setting operation of the memory device, at least one other page of the cell array stores replica IDR data including inverted bit values of the IDR data, and the control logic controls a recovery operation for repairing errors in the IDR data by reading the replica IDR data when a read fail of the IDR data occurs.

公开(公告)号：US11895837B2

公开(公告)日：2024-02-06

申请号：US17737164

申请日：2022-05-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Janggn Yun ,  Jaeduk Lee

IPC: H10B41/50 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

CPC classification number: H10B41/50 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes stacked on the substrate, a channel structure penetrating the plurality of gate electrodes and including a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate in the memory cell region, a dummy channel structure penetrating the plurality of gate electrodes and including a dummy channel layer extending in the vertical direction in the connection region, a first semiconductor layer disposed between the substrate and a lowermost one of the plurality of gate electrodes and surrounding the channel structure in the memory cell region, and an insulating separation structure disposed between the substrate and the lowermost one of the plurality of gate electrodes and surrounding the dummy channel layer.

公开(公告)号：US11699490B2

公开(公告)日：2023-07-11

申请号：US17220218

申请日：2021-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soyeong Gwak ,  Raeyoung Lee ,  Jinkyu Kang ,  Sejun Park ,  Changhwan Shin ,  Jaeduk Lee ,  Woojae Jang

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/26 ,  G11C7/10 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/16 ,  G11C7/106 ,  G11C7/1087 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/349

Abstract: An operating method of a storage device includes reading a wear-out pattern of a memory block when a controller determines the memory block is a re-use memory block of a non-volatile memory device; selecting an operation mode corresponding to the read wear-out pattern using the controller; and transmitting the selected operation mode to the non-volatile memory device using the controller.

公开(公告)号：US11569262B2

公开(公告)日：2023-01-31

申请号：US17036034

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Janggn Yun ,  Jaeduk Lee ,  Dongwhee Kwon

IPC: H01L27/11582 ,  H01L27/24 ,  H01L23/535 ,  H01L27/11556

Abstract: A semiconductor device includes a first stacked structure and a second stacked structure spaced apart from each other on a substrate, and a plurality of separation structures and a plurality of vertical memory structures alternately arranged between the first stacked structure and the second stacked structure in a first direction parallel to an upper surface of the substrate. Each of the first and second stacked structures includes a plurality of interlayer insulating layers and a plurality of gate layers alternately repeatedly stacked on the lower structure. Each of the vertical memory structures includes a first data storage structure facing the first stacked structure and a second data storage structure facing the second stacked structure. Side surfaces of the first and second stacked structures facing the vertical memory structures are concave in a plan view.

公开(公告)号：US11380711B2

公开(公告)日：2022-07-05

申请号：US17154583

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon Lee ,  Sungsu Moon ,  Jaeduk Lee ,  Ikhyung Joo

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/08 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation film and providing a first channel region; a first source/drain region in the active region on first and second sides of the first channel region; a gate structure having a first gate insulating film, a shared gate electrode, and a second gate insulating film, sequentially arranged on the active region; a cover semiconductor layer on the second gate insulating film and electrically separated from the active region to provide a second channel region; a second source/drain region in the cover semiconductor layer on first and second sides of the second channel region first and second source/drain contacts respectively connected to the first and second source/drain regions; and a shared gate contact connected to the shared gate electrode.

公开(公告)号：US11257841B2

公开(公告)日：2022-02-22

申请号：US16787195

申请日：2020-02-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Kyu Kang ,  Woojae Jang ,  Changsub Lee ,  Sejun Park ,  Jaeduk Lee ,  Jung Hoon Lee

IPC: H01L27/11582 ,  H01L29/792 ,  H01L29/423 ,  H01L29/78

Abstract: A three-dimensional semiconductor memory device including a stack structure including gate structures and first dielectric patterns alternately stacked, a vertical channel penetrating the stack structure, and a charge storage layer extending from between the vertical channel and the first gate structures to between the vertical channel and the first dielectric patterns. The gate structures include first gate structures having a top surface and a bottom surface facing each other and having different width. The charge storage layer includes first segments between the vertical channel and the first gate structures, and second segments between the vertical channel and the first dielectric patterns. A thickness of the first segments is greater than a thickness of the second segments. One of the width of the top surface and the width of bottom surface of each first gate structure is the same as that of a first dielectric pattern on the first gate structure.

公开(公告)号：US10566233B2

公开(公告)日：2020-02-18

申请号：US16534195

申请日：2019-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC: H01L21/00 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L23/532 ,  H01L23/522 ,  H01L27/1157 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

公开(公告)号：US20180350833A1

公开(公告)日：2018-12-06

申请号：US16039975

申请日：2018-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk Lee ,  Youngwoo PARK

IPC: H01L27/11582 ,  H01L27/06 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L27/0688 ,  H01L27/11573

Abstract: The inventive concepts relate to a semiconductor memory device. The semiconductor memory device includes a substrate including a circuit region and first and second connection regions respectively disposed at both sides of the circuit region opposite to each other, a logic structure including a logic circuit disposed on the circuit region and a lower insulating layer covering the logic circuit, and a memory structure on the logic structure. The logic circuit includes a first page buffer disposed adjacently to the first connection region and a second page buffer disposed adjacently to the second connection region. The memory structure includes bit lines extending onto at least one of the first and second connection regions.