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    SEMICONDUCTOR MEMORY DEVICES
    23.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20190051652A1

    公开(公告)日：2019-02-14

    申请号：US15952308

    申请日：2018-04-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung Kim ,  Min Hee Cho ,  Bong-Soo Kim ,  Junsoo Kim ,  Satoru Yamada ,  Wonsok Lee ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L29/06 ,  H01L29/49 ,  H01L21/28

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

    Semiconductor memory device and a method of fabricating the same
    26.
    发明授权
    Semiconductor memory device and a method of fabricating the same 有权

    公开(公告)号：US12048141B2

    公开(公告)日：2024-07-23

    申请号：US17574666

    申请日：2022-01-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok Lee ,  Hui-Jung Kim ,  Min Hee Cho

    IPC: H10B12/00 ,  H01L29/786

    CPC classification number: H10B12/30 ,  H01L29/78693 ,  H10B12/03 ,  H10B12/05 ,  H10B12/50

    Abstract: A semiconductor memory device including: a stack structure including a plurality of layers that are vertically stacked on a substrate, each of the plurality of layers including a word line, a channel layer, and a data storage element electrically connected to the channel layer; and a bit line that vertically extends on one side of the stack structure, wherein the word line includes: a first conductive line that extends in a first direction; and a gate electrode that protrudes in a second direction from the first conductive line, the second direction intersecting the first direction, wherein the channel layer is on the gate electrode, and wherein the bit line includes a connection part electrically connected to the channel layer.

    Three-dimensional semiconductor device with a bit line perpendicular to a substrate
    28.
    发明授权
    Three-dimensional semiconductor device with a bit line perpendicular to a substrate 有权

    公开(公告)号：US11563005B2

    公开(公告)日：2023-01-24

    申请号：US16930398

    申请日：2020-07-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minsu Lee ,  Kiseok Lee ,  Minwoo Song ,  Hyun-Sil Oh ,  Min Hee Cho

    IPC: H01L27/108 ,  G11C8/14 ,  G11C7/18

    Abstract: A three-dimensional semiconductor device includes a first channel pattern on and spaced apart from a substrate, the first channel pattern having a first end and a second end that are spaced apart from each other in a first direction parallel to a top surface of the substrate, and a first sidewall and a second sidewall connecting between the first end and the second end, the first and second sidewalls being spaced apart from each other in a second direction parallel to the top surface of the substrate, the second direction intersecting the first direction, a bit line in contact with the first end of the first channel pattern, the bit line extending in a third direction perpendicular to the top surface of the substrate, and a first gate electrode adjacent to the first sidewall of the first channel pattern.

    Semiconductor device including oxide semiconductor layer
    29.
    发明授权
    Semiconductor device including oxide semiconductor layer 有权

    公开(公告)号：US11532707B2

    公开(公告)日：2022-12-20

    申请号：US16796273

    申请日：2020-02-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Woo Bin Song ,  Sang Woo Lee ,  Min Hee Cho

    IPC: H01L29/786 ,  H01L29/08 ,  H01L29/51 ,  H01L29/417 ,  H01L29/45 ,  H01L29/24 ,  H01L29/267

    Abstract: Aspects of the present inventive concept provide a semiconductor device capable of enhancing performance and reliability through source/drain engineering in a transistor including an oxide semiconductor layer. The semiconductor device includes a substrate, a metal oxide layer disposed on the substrate, a source/drain pattern being in contact with the metal oxide layer and including a portion protruding from a top surface of the metal oxide layer, a plurality of gate structures disposed on the metal oxide layer with the source/drain pattern interposed therebetween and each including gate spacers and an insulating material layer, the insulating material layer being in contact with the metal oxide layer, and not extending along a top surface of the source/drain pattern, and a contact disposed on the source/drain pattern, the contact being connected to the source/drain pattern.

    Semiconductor memory device
    30.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11488956B2

    公开(公告)日：2022-11-01

    申请号：US17313570

    申请日：2021-05-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Beomyong Hwang ,  Min Hee Cho ,  Hei Seung Kim ,  Mirco Cantoro ,  Hyunmog Park ,  Woo Bin Song ,  Sang Woo Lee

    IPC: H01L27/10 ,  H01L27/108 ,  G11C11/402

    Abstract: A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.

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