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    Semiconductor memory devices
    1.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US11195836B2

    公开(公告)日：2021-12-07

    申请号：US16732925

    申请日：2020-01-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung Kim ,  Min Hee Cho ,  Junsoo Kim ,  Taehyun An ,  Dongsoo Woo ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

    Abstract: A semiconductor memory device includes a stack structure having a plurality of layers vertically stacked on a substrate, each layer including, a first bit line and a gate line extending in a first direction, a first semiconductor pattern extending in a second direction between the first bit line and the gate line, the second direction intersecting the first direction, and a second semiconductor pattern adjacent to the gate line across a first gate insulating layer, the second semiconductor pattern extending in the first direction, a first word line adjacent to the first semiconductor pattern and vertically extending in a third direction from the substrate, a second bit line connected to an end of the second semiconductor pattern and vertically extending in the third direction from the substrate, and a second word line connected to another end of the second semiconductor pattern and vertically extending in the third direction.

    SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210257369A1

    公开(公告)日：2021-08-19

    申请号：US17313570

    申请日：2021-05-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Beomyong Hwang ,  Min Hee Cho ,  Hei Seung Kim ,  Mirco Cantoro ,  Hyunmog Park ,  Woo Bin Song ,  Sang Woo Lee

    IPC: H01L27/108 ,  G11C11/402

    Abstract: A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.

    SEMICONDUCTOR MEMORY DEVICES
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20200219885A1

    公开(公告)日：2020-07-09

    申请号：US16820006

    申请日：2020-03-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung Kim ,  Min Hee Cho ,  Bong-Soo Kim ,  Junsoo Kim ,  Satoru Yamada ,  Wonsok Lee ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L21/28 ,  H01L29/49 ,  H01L29/06

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

    SEMICONDUCTOR DEVICE INCLUDING A GATE INSULATION PATTERN AND A GATE ELECTRODE PATTERN
    4.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING A GATE INSULATION PATTERN AND A GATE ELECTRODE PATTERN 审中-公开

    公开(公告)号：US20190067278A1

    公开(公告)日：2019-02-28

    申请号：US15952798

    申请日：2018-04-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeoungwon Seo ,  Wonsok Lee ,  Min Hee Cho ,  Hyun-Sook Byun

    IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49

    Abstract: A semiconductor device includes a substrate including an active region defined by a device isolation layer. A word line structure is in a trench formed in an upper portion of the substrate. The word line structure includes a gate insulation pattern covering an inner surface of the trench. A gate electrode pattern is on the gate insulation pattern. A first work function pattern is between the gate insulation pattern and the gate electrode pattern. A second work function pattern is on the first work function pattern and extends along a side surface of the gate electrode pattern. The first work function pattern has a top surface at a level below that of a bottom surface of the gate electrode pattern. The first work function pattern has a work function greater than that of the second work function pattern.

    Semiconductor device including dummy metal
    5.
    发明授权
    Semiconductor device including dummy metal 有权

    公开(公告)号：US10032780B2

    公开(公告)日：2018-07-24

    申请号：US15139444

    申请日：2016-04-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Min Hee Cho ,  Satoru Yamada ,  Sung-Sam Lee ,  Jung-Bun Lee

    IPC: H01L27/108 ,  H01L23/522

    Abstract: A semiconductor device may include a plurality of dummy wirings formed on a substrate at different vertical levels and electrically floated and a plurality of dummy contact plugs each electrically connected between two adjacent dummy wirings of the plurality of dummy wiring of the plurality of dummy wirings. No dummy wiring of the plurality of dummy wirings is electrically connected to a terminal of any one of a plurality of transistors included in the substrate.

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US12075611B2

    公开(公告)日：2024-08-27

    申请号：US17481583

    申请日：2021-09-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Wonsok Lee ,  Min Tae Ryu ,  Woo Bin Song ,  Kiseok Lee ,  Minsu Lee ,  Min Hee Cho

    IPC: H10B12/00 ,  G11C5/06 ,  H01L29/06

    CPC classification number: H10B12/315 ,  G11C5/063 ,  H01L29/0607 ,  H10B12/05 ,  H10B12/50

    Abstract: A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.

    Semiconductor device including a gate insulation pattern and a gate electrode pattern
    9.
    发明授权
    Semiconductor device including a gate insulation pattern and a gate electrode pattern 有权

    公开(公告)号：US10811408B2

    公开(公告)日：2020-10-20

    申请号：US15952798

    申请日：2018-04-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyeoungwon Seo ,  Wonsok Lee ,  Min Hee Cho ,  Hyun-Sook Byun

    IPC: H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78

    Abstract: A semiconductor device includes a substrate including an active region defined by a device isolation layer. A word line structure is in a trench formed in an upper portion of the substrate. The word line structure includes a gate insulation pattern covering an inner surface of the trench. A gate electrode pattern is on the gate insulation pattern. A first work function pattern is between the gate insulation pattern and the gate electrode pattern. A second work function pattern is on the first work function pattern and extends along a side surface of the gate electrode pattern. The first work function pattern has a top surface at a level below that of a bottom surface of the gate electrode pattern. The first work function pattern has a work function greater than that of the second work function pattern.

    Semiconductor device
    10.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10199379B2

    公开(公告)日：2019-02-05

    申请号：US15835071

    申请日：2017-12-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Min Hee Cho ,  Woo Song Ahn ,  Min Su Choi ,  Satoru Yamada ,  Jun Soo Kim ,  Sung Sam Lee

    IPC: H01L29/51 ,  H01L27/108 ,  H01L49/02 ,  H01L29/06 ,  H01L29/423

    Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.

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