公开(公告)号：US20220093179A1

公开(公告)日：2022-03-24

申请号：US17234955

申请日：2021-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yohan Lee ,  Sangwan Nam ,  Sangwon Park

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/08 ,  G11C16/04

Abstract: A memory device includes memory blocks, each including memory cells, and peripheral circuits that control the memory blocks and execute an erase operation for each of the memory blocks. Each memory block includes word lines stacked on a substrate, channel structures extending perpendicular to an upper surface of the substrate and penetrating through the word lines, and a source region disposed on the substrate and connected to the channel structures. During an erase operation in which an erase voltage is input to the source region of a target memory block, the peripheral circuits reduce a voltage of a first word line from a first bias voltage to a second bias voltage at a first time and reduce a voltage of a second word line, different from the first word line, from a third bias voltage to a fourth bias voltage at a second time different from the first in time.

公开(公告)号：US20210098072A1

公开(公告)日：2021-04-01

申请号：US17022967

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G11C29/00 ,  G11C7/10 ,  G11C29/18 ,  G11C29/44 ,  G11C29/12

Abstract: A nonvolatile memory device includes memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, is connected to the memory cell region by the first metal pad and the second metal pad and includes including an address decoder and a page buffer circuit located on a first substrate. A memory cell array is provided in the memory cell region, which includes a first vertical structure on a second substrate. The first vertical structure includes first sub-blocks and first via areas in which one or more through-hole vias are provided, and through-hole vias pass through the first vertical structure. A control circuit in the peripheral circuit region groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US10057038B2

公开(公告)日：2018-08-21

申请号：US15153132

申请日：2016-05-12

Applicant: Samsung Electronics Co., Ltd. ,  Industry-Academic Cooperation Foundation Yonsei University

Inventor： Hyoungju Ji ,  Sanggeun Lee ,  Younsun Kim ,  Chungyong Lee ,  Sangwon Park

IPC: H04L5/14 ,  H04L5/00 ,  H04W72/04 ,  H04W24/08 ,  H04L1/12 ,  H04W72/12

CPC classification number: H04L5/0055 ,  H04L1/12 ,  H04L1/1822 ,  H04L1/1887 ,  H04L5/1469 ,  H04W72/1289

Abstract: A method and apparatus for feedback in a mobile communication system are provided. The method of feedback transmission for a user equipment (UE) in a wireless communication system includes receiving control information indicating whether a subframe of an uplink band is allocated for a downlink from a base station (BS), receiving data from the BS in at least three subframes according to the control information, and sending the BS feedback for the data received in the at least three subframes using transmission time interval (TTI) bundling.

公开(公告)号：USD1070206S1

公开(公告)日：2025-04-08

申请号：US29906689

申请日：2023-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Seungwook Suh ,  Jichang Kang ,  Jinsook Park ,  Euikyun Koh ,  Sangwon Park ,  Seongju Kim

公开(公告)号：US12217802B2

公开(公告)日：2025-02-04

申请号：US17648311

申请日：2022-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyong Park ,  Sangwon Park ,  Dongjin Shin ,  Suchang Jeon ,  Seungyong Choi

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/20

Abstract: A non-volatile memory device includes a meta area having a first region storing first initial data, and second regions storing second initial data, different from each other; a user area configured to store user data; an initialization register configured to store the first initial data or update the second initial data in whole or in part; and control logic configured to perform a read operation, a program operation, or an erase operation using the initial data stored in the initialization register.

公开(公告)号：US11830558B2

公开(公告)日：2023-11-28

申请号：US17742142

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwon Shim ,  Sangwon Park ,  Bongsoon Lim ,  Yoonhee Choi

IPC: G11C16/30 ,  G11C5/14 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C16/30 ,  G11C5/14 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit disposed below the first memory cell array; a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit disposed below the second memory cell array; and a pad area including a power wiring. The first and second memory areas respectively include first and second local lockout circuits separately determining whether to lock out of each of the memory areas. The first and second memory areas are included in a single semiconductor chip to share the pad area, and the first and second memory areas operate individually. Accordingly, in the memory device, unnecessary data loss may be reduced by selectively stopping an operation of only a memory area requiring recovery.

公开(公告)号：US20230100548A1

公开(公告)日：2023-03-30

申请号：US17742879

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kuihan Ko ,  Sangwon Park ,  Minyong Kim ,  Jekyung Choi ,  Junho Choi

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/10 ,  G11C16/26

Abstract: A non-volatile memory device is provided. The memory device includes: word lines stacked on a substrate; a string select lines on the word lines, the string select lines being spaced apart from each other in a first horizontal direction and extending in a second horizontal direction; and a memory cell array including memory blocks, each of which includes memory cells connected to the word lines and the string select lines. The string select lines include a first string select line, and a second string select line which is farther from a word line cut region than the first string select line, and a program operation performed on second memory cells connected to a selected word line and the second string select line is performed before a program operation performed on first memory cells connected to the selected word line and the first string select line.

公开(公告)号：US20230013747A1

公开(公告)日：2023-01-19

申请号：US17935502

申请日：2022-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G06F11/20 ,  G11C16/04 ,  G11C16/08

Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US11501847B2

公开(公告)日：2022-11-15

申请号：US17022967

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G11C16/10 ,  G11C29/00 ,  G11C29/44 ,  G11C29/18 ,  G11C7/10 ,  G11C29/12

Abstract: A nonvolatile memory device includes memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, is connected to the memory cell region by the first metal pad and the second metal pad and includes including an address decoder and a page buffer circuit located on a first substrate. A memory cell array is provided in the memory cell region, which includes a first vertical structure on a second substrate. The first vertical structure includes first sub-blocks and first via areas in which one or more through-hole vias are provided, and through-hole vias pass through the first vertical structure. A control circuit in the peripheral circuit region groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US11467932B2

公开(公告)日：2022-10-11

申请号：US16865948

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G11C16/10 ,  G06F11/20 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11556 ,  H01L27/11582

Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.