公开(公告)号：US12211698B2

公开(公告)日：2025-01-28

申请号：US16889448

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Siao-Shan Wang ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/308 ,  G03F7/26 ,  G03F7/40 ,  H01L21/027

Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate, where the patterned resist layer has a first line width roughness. In various embodiments, the patterned resist layer is coated with a treatment material, where a first portion of the treatment material bonds to surfaces of the patterned resist layer. In some embodiments, a second portion of the treatment material (e.g., not bonded to surfaces of the patterned resist layer) is removed, thereby providing a treated patterned resist layer, where the treated patterned resist layer has a second line width roughness less than the first line width roughness.

公开(公告)号：US11854860B2

公开(公告)日：2023-12-26

申请号：US18055784

申请日：2022-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao Hung ,  Ping-Cheng Ko ,  Tzu-Yang Lin ,  Fang-Yu Liu ,  Cheng-Han Wu

IPC: H01L21/687 ,  H01L21/67 ,  H01L21/677 ,  H01L21/66 ,  H05F1/00

CPC classification number: H01L21/68757 ,  H01L21/6719 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67242 ,  H01L21/67742 ,  H01L22/10 ,  H05F1/00

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

公开(公告)号：US11650500B2

公开(公告)日：2023-05-16

申请号：US17007897

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Keng-Chu Lin ,  Joung-Wei Liou ,  Cheng-Han Wu ,  Ya Hui Chang

IPC: G03F7/16 ,  G03F7/038 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  G03F7/039 ,  G03F7/11 ,  G03F7/20 ,  G03F7/32

CPC classification number: G03F7/0388 ,  G03F7/038 ,  G03F7/0382 ,  G03F7/0397 ,  G03F7/11 ,  G03F7/167 ,  G03F7/2041 ,  G03F7/322 ,  G03F7/325 ,  H01L21/0271 ,  H01L21/31144 ,  H01L21/32139

Abstract: A system and method for depositing a photoresist and utilizing the photoresist are provided. In an embodiment a deposition chamber is utilized along with a first precursor material comprising carbon-carbon double bonds and a second precursor material comprising repeating units to deposit the photoresist onto a substrate. The first precursor material is turned into a plasma in a remote plasma chamber prior to being introduced into the deposition chamber. The resulting photoresist comprises a carbon backbone with carbon-carbon double bonds.

公开(公告)号：US11387232B2

公开(公告)日：2022-07-12

申请号：US15628728

申请日：2017-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Han Wu ,  Chie-Iuan Lin ,  Kuei-Ming Chang ,  Rei-Jay Hsieh

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/265

Abstract: A semiconductor device includes a substrate; a first gate stack disposed on the substrate; a second gate stack disposed on the substrate, wherein a metal component of the first gate stack is different from a metal component of the second gate stack; and a dielectric structure disposed over the substrate and between the first gate stack and the second gate stack, in which the dielectric structure is separated from the first gate stack and the second gate stack, and a distance between the dielectric structure and the first gate stack is substantially equal to a distance between the dielectric structure and the second gate stack.

公开(公告)号：US11378884B2

公开(公告)日：2022-07-05

申请号：US16725884

申请日：2019-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Liu ,  Ya-Ching Chang ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/38 ,  G03F7/30 ,  G03F7/039 ,  G03F7/32 ,  G03F7/20

Abstract: The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a photoresist layer over a substrate. The photoresist layer includes at least an acid labile group (ALG) and a thermo-base generator (TBG). The method further includes exposing a portion of the photoresist layer to a radiation and performing a baking process after the exposing of the portion of the photoresist layer. The TBG releases a base during the performing of the baking process, resulting in a chemical reaction between the ALG and the base. The method further includes removing an unexposed portion of the photoresist layer, resulting in a patterned photoresist layer.

公开(公告)号：US11022886B2

公开(公告)日：2021-06-01

申请号：US15597734

申请日：2017-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hui Weng ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/16 ,  H01L21/02 ,  H01L21/321 ,  H01L21/308 ,  H01L21/027 ,  H01L21/3105 ,  G03F7/039 ,  G03F7/38 ,  H01L21/311

Abstract: The present disclosure provides a method for planarization. The method includes providing a substrate having a top surface and a trench recessed from the top surface; coating a sensitive material layer on the top surface of the substrate, wherein the sensitive material layer fills in the trench; performing an activation treatment to the sensitive material layer so that portions of the material layer are chemically changed; and performing a wet chemical process to the sensitive material layer so that top portions of the sensitive material layer above the trench are removed, wherein remaining portions of the sensitive material layer have top surfaces substantially coplanar with the top surface of the substrate.

公开(公告)号：US10649339B2

公开(公告)日：2020-05-12

申请号：US15482315

申请日：2017-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Ching Chang ,  Chen-Yu Liu ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/20 ,  G03F7/039 ,  G03F7/32 ,  G03F7/16 ,  G03F7/38

Abstract: A resist material and methods for forming a semiconductor structure including using the resist material are provided. The method for forming a semiconductor structure includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed portion of the resist layer by performing an exposure process. The method for forming a semiconductor structure further includes developing the resist layer in a developer. In addition, the resist layer is made of a resist material including a photosensitive polymer and a contrast promoter, and a protected functional group of the photosensitive polymer is deprotected to form a deprotected functional group during the exposure process, and a functional group of the contrast promoter bonds to the deprotected functional group of the photosensitive polymer.

公开(公告)号：US10558120B2

公开(公告)日：2020-02-11

申请号：US15806663

申请日：2017-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Zhan Zhou ,  Heng-Jen Lee ,  Hsu-Yuan Liu ,  Yu-Chen Huang ,  Cheng-Han Wu ,  Shih-Che Wang ,  Ho-Yung David Hwang

IPC: G03F7/16 ,  B67D7/02 ,  B67D7/36 ,  B67D7/78

Abstract: A photolithography system includes a variable-volume buffer tank, a dispensing system connected to the buffer tank, and a valve configured to release gas from a head space of the buffer tank while blocking the release of liquid from the head space. A storage container has an opening at the bottom and drains to the buffer tank through that opening. The buffer tank has a storage capacity sufficient to receive the full contents of the storage container. The system supplies chemical solutions to the dispensing system while keeping the chemical solutions from contact with air and other gases.

公开(公告)号：US10520833B1

公开(公告)日：2019-12-31

申请号：US16035354

申请日：2018-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hui Weng ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03B27/58 ,  G03F7/20

Abstract: Semiconductor systems, apparatuses and methods are provided. In one embodiment, an extreme ultraviolet lithography system includes a substrate stage configured to secure a substrate at a first vertical level, wherein the substrate is deposited with a resist layer thereon; at least one electrode positioned at a second vertical level above the first vertical level; and a power source configured to apply an electric field across the at least one electrode and the substrate stage, including across a thickness of the resist layer when the substrate is secured on the substrate stage.

公开(公告)号：US20190004430A1

公开(公告)日：2019-01-03

申请号：US15639033

申请日：2017-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hui Weng ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/40

CPC classification number: G03F7/40 ,  G03F7/0392

Abstract: The present disclosure provides lithography resist materials and corresponding lithography techniques for improving lithography resolution, in particular, by reducing swelling of resist layers during development. An exemplary lithography method includes performing a treatment process on a resist layer to cause cross-linking of acid labile group components of the resist layer via cross-linkable functional components, performing an exposure process on the resist layer, and performing a development process on the resist layer. In some implementations, the resist layer includes an exposed portion and an unexposed portion after the exposure process, and the treatment process reduces solubility of the unexposed portion to a developer used during the development process by increasing a molecular weight of a polymer in the unexposed portion. The treatment process is performed before or after the exposure process. The treatment process can include performing a thermal treatment and/or an electromagnetic wave treatment to heat the resist layer.