公开(公告)号：US09560773B2

公开(公告)日：2017-01-31

申请号：US14809117

申请日：2015-07-24

Applicant: Tessera, Inc.

Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Belgacem Haba ,  Piyush Savalia ,  Craig Mitchell

IPC: H05K1/03 ,  H05K1/09 ,  H05K3/40 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/056 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/013 ,  H05K1/09 ,  H05K3/4007 ,  H05K2201/032 ,  H05K2201/0326 ,  H05K2201/0338

Abstract: An electrical connection structure includes a variable-composition nickel alloy layer with a minor constituent selected from a group consisting of boron, carbon, phosphorus, and tungsten, wherein at least over a portion of a conductive substrate, the concentration of the minor constituent decreases throughout the variable-composition nickel alloy layer in a direction from the bottom surface of the variable-composition nickel alloy layer to the top surface of the variable-composition nickel alloy layer.

Abstract translation: 电连接结构包括具有选自硼，碳，磷和钨的次要成分的可变组成镍合金层，其中至少在一部分导电基底上，次要成分的浓度全部降低 该可变组成镍合金层在从可变组成镍合金层的底面到可变组成镍合金层的顶表面的方向上。

公开(公告)号：US09355959B2

公开(公告)日：2016-05-31

申请号：US14094621

申请日：2013-12-02

Applicant: Tessera, Inc.

Inventor： Vage Oganesian ,  Ilyas Mohammed ,  Craig Mitchell ,  Belgacem Haba ,  Piyush Savalia

IPC: H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L27/146 ,  H01L29/06 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5384 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14645 ,  H01L29/0657 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81805 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.

公开(公告)号：US09269692B2

公开(公告)日：2016-02-23

申请号：US14224379

申请日：2014-03-25

Applicant: Tessera, Inc.

Inventor： Vage Oganesian ,  Belgacem Haba ,  Ilyas Mohammed ,  Craig Mitchell ,  Piyush Savalia

IPC: H01L21/4763 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L21/78 ,  H01L23/14

CPC classification number: H01L23/481 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/145 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/83 ,  H01L2224/9202 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element. A conductive element extends within the first and second openings and contacts the at least one conductive pad.

Abstract translation: 提供了一种微电子组件，其包括基本上由半导体或无机电介质材料中的至少一种构成的第一元件，该介电材料具有面向并附着到微电子元件的主表面的表面，在该电子元件的主表面处暴露多个导电焊盘，该微电子元件具有 其中有源半导体器件。 第一开口从第一元件的暴露表面延伸到附接到微电子元件的表面，并且第二开口从第一开口延伸到第一导电焊盘中，其中第一和第二开口相交，其中内表面 第一和第二开口相对于微电子元件的主表面以不同的角度延伸。 导电元件在第一和第二开口内延伸并接触至少一个导电垫。

公开(公告)号：US09018769B2

公开(公告)日：2015-04-28

申请号：US14243484

申请日：2014-04-02

Applicant: Tessera, Inc.

Inventor： Vage Oganesian ,  Belgacem Haba ,  Ilyas Mohammed ,  Craig Mitchell ,  Piyush Savalia

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/80 ,  H01L31/112 ,  H01L29/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/76879 ,  H01L21/76802 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/4985 ,  H01L23/5226 ,  H01L24/06 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.

Abstract translation: 提供了在基板上形成导电元件的方法和所得到的组件。 该方法包括在覆盖设置在基板上的电介质区域上的牺牲层中形成凹槽。 槽优选地沿着衬底的倾斜表面延伸。 牺牲层优选通过非光刻方法去除，例如用激光烧蚀，机械研磨或喷砂。 在沟槽中形成导电元件。 可以形成凹槽。 凹槽和导电元件可以沿着衬底的任何表面形成，包括在其中形成的沟槽和通孔内，并且可以连接到衬底的前表面和/或后表面上的导电焊盘。 导电元件优选通过电镀形成，并且可以或可以不与基板的表面一致。

公开(公告)号：US20150079733A1

公开(公告)日：2015-03-19

申请号：US14492964

申请日：2014-09-22

Applicant: Tessera, Inc.

Inventor： Vage Oganesian ,  Belgacem Haba ,  Ilyas Mohammed ,  Piyush Savalia ,  Craig Mitchell

IPC: H01L25/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/06524 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/00

Abstract: A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having at least a portion having a thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements.

Abstract translation: 微电子组件可以包括例如电介质或半导体材料的第一，第二和第三堆叠的基本平坦的元件，并且其可以具有小于10ppm /℃的CTE。组件可以是微电子封装，并且可以并入有源半导体 在第一，第二或第三元件中的一个，两个或更多个元件中的装置可以协同地作为系统级封装。 在一个示例中，具有厚度小于10微米的至少一部分的导电元件可以通过电镀形成，并且可以电连接第一，第二或第三元件中的两个或更多个。 导电元件可以完全位于另一个基本上平面的元件的表面之下。

公开(公告)号：US08829680B2

公开(公告)日：2014-09-09

申请号：US14089057

申请日：2013-11-25

Applicant: Tessera, Inc.

Inventor： Cyprian Emeka Uzoh ,  Belgacem Haba ,  Craig Mitchell

IPC: H01L21/32 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/1094 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有覆盖在不同材料中的互连结构的顶表面和侧壁的部分。 在一些实施例中，异种材料可以是导电材料或纳米合金。 互连结构可以通过去除互连结构的一部分并且用不同材料覆盖互连结构来形成。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

公开(公告)号：US08709913B2

公开(公告)日：2014-04-29

申请号：US13939725

申请日：2013-07-11

Applicant: Tessera, Inc.

Inventor： Vage Oganesian ,  Belgacem Haba ,  Ilyas Mohammed ,  Piyush Savalia ,  Craig Mitchell

IPC: H01L21/30

CPC classification number: H01L25/00 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05186 ,  H01L2224/0519 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/0613 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06505 ,  H01L2224/116 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/276 ,  H01L2224/29023 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32148 ,  H01L2224/32238 ,  H01L2224/73103 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/8323 ,  H01L2224/83815 ,  H01L2224/8383 ,  H01L2224/9202 ,  H01L2224/9221 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/35 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Abstract translation: 公开了两种元件的微电子组件及其形成方法。 微电子元件包括主表面和介电层以及在主表面处暴露的至少一个接合焊盘。 微电子元件可以包含多个有源电路元件。 沉积第一金属层，覆盖至少一个接合焊盘和电介质层。 提供了具有沉积在其上的第二金属层的第二元件，并且第一金属层与第二金属层接合。 组件可以沿着切割通道切割成各自包括芯片的单元。

公开(公告)号：US20140097546A1

公开(公告)日：2014-04-10

申请号：US14104407

申请日：2013-12-12

Applicant: Tessera, Inc.

Inventor： Vage Oganesian ,  Belgacem Haba ,  Ilyas Mohammed ,  Craig Mitchell ,  Piyush Savalia

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/6622 ,  H01L2224/05009 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

Abstract translation: 微电子单元包括基本上由半导体材料组成的半导体元件，其具有前表面，后表面，与前表面相邻的多个有源半导体器件，在前表面暴露的多个导电焊盘，以及延伸穿过 半导体元件。 至少一个导电焊盘可以至少部分地覆盖开口并且可以与至少一个有源半导体器件电连接。 微电子单元还可以包括暴露在后表面处以与外部部件连接的第一导电元件，第一导电元件延伸穿过开口并与至少一个导电焊盘电连接，第二导电元件延伸穿过开口 并与第一导电元件绝缘。 至少一个导电焊盘可以覆盖在第二导电元件的周边边缘上。

公开(公告)号：US20140084485A1

公开(公告)日：2014-03-27

申请号：US14089057

申请日：2013-11-25

Applicant: Tessera, Inc.

Inventor： Cyprian Emeka Uzoh ,  Belgacem Haba ,  Craig Mitchell

IPC: H01L23/528

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/1094 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有覆盖在不同材料中的互连结构的顶表面和侧壁的部分。 在一些实施例中，异种材料可以是导电材料或纳米合金。 互连结构可以通过去除互连结构的一部分并且用不同材料覆盖互连结构来形成。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

公开(公告)号：US10559494B2

公开(公告)日：2020-02-11

申请号：US15971466

申请日：2018-05-04

Applicant: Tessera, Inc.

Inventor： Vage Oganesian ,  Belgacem Haba ,  Craig Mitchell ,  Ilyas Mohammed ,  Piyush Savalia

IPC: H01L21/768 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L25/16 ,  H01L25/11 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498

Abstract: A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.