公开(公告)号：US11626271B2

公开(公告)日：2023-04-11

申请号：US17325913

申请日：2021-05-20

Applicant: Tokyo Electron Limited

Inventor： Scott Lefevre ,  Akiteru Ko

IPC: H01J37/32 ,  H01L21/683 ,  B08B7/00

Abstract: Embodiments are disclosed for reducing substrate breaks which result from inadequate de-chucking. Contaminants are removed from the surface of a chuck by exposing the chuck to a plasma process that comprises a hydrogen (H)-containing plasma. The chuck is subjected to the hydrogen-based plasma when no substrate is on the chuck. In one embodiment, the plasma is a hydrocarbon-based plasma. Hydrogen in the hydrocarbon plasma may react with and remove the contaminants. The process may further include an additional plasma step for removal of any newly formed materials that may result from the hydrocarbon plasma. The removal step may be, for example, a subsequent plasma ash step. In one embodiment, the chuck is an electrostatic chuck and the contaminants comprise fluorine. By removing contaminants from the chuck surface, improved substrate de-chucking occurs. This improvement correspondingly leads to less substrate breakage when removing substrates from the chuck.

公开(公告)号：US11515160B2

公开(公告)日：2022-11-29

申请号：US16836239

申请日：2020-03-31

Applicant: Tokyo Electron Limited

Inventor： Akiteru Ko

IPC: H01L21/033 ,  C23C14/34 ,  G03F7/20 ,  H01L29/66 ,  G03F7/16 ,  G03F7/30

Abstract: A method includes providing a substrate including mandrels of a first material positioned on an underlying layer. Each of the mandrels includes a first sidewall and an opposing second sidewall. The method further includes forming sidewall spacers made of a second material and including a first sidewall spacer abutting each respective first sidewall and a second sidewall spacer abutting each respective second sidewall. The mandrels extend above top surfaces of the sidewall spacers. The method also includes forming first capped sidewall spacers by depositing a third material on the first sidewall spacers without depositing on the second sidewall spacers, forming second capped sidewall spacers by depositing a fourth material on the second sidewall spacers without depositing on the first sidewall spacers, and selectively removing at least one of the first material, the second material, the third material, and the fourth material to uncover an exposed portion of the underlying layer.

公开(公告)号：US20210398784A1

公开(公告)日：2021-12-23

申请号：US17325913

申请日：2021-05-20

Applicant: Tokyo Electron Limited

Inventor： Scott Lefevre ,  Akiteru Ko

IPC: H01J37/32 ,  H01L21/683 ,  B08B7/00

Abstract: Embodiments are disclosed for reducing substrate breaks which result from inadequate de-chucking. Contaminants are removed from the surface of a chuck by exposing the chuck to a plasma process that comprises a hydrogen (H)-containing plasma. The chuck is subjected to the hydrogen-based plasma when no substrate is on the chuck. In one embodiment, the plasma is a hydrocarbon-based plasma. Hydrogen in the hydrocarbon plasma may react with and remove the contaminants. The process may further include an additional plasma step for removal of any newly formed materials that may result from the hydrocarbon plasma. The removal step may be, for example, a subsequent plasma ash step. In one embodiment, the chuck is an electrostatic chuck and the contaminants comprise fluorine. By removing contaminants from the chuck surface, improved substrate de-chucking occurs. This improvement correspondingly leads to less substrate breakage when removing substrates from the chuck.

公开(公告)号：US11049721B2

公开(公告)日：2021-06-29

申请号：US16561350

申请日：2019-09-05

Applicant: Tokyo Electron Limited

Inventor： Toshiharu Wada ,  Akiteru Ko ,  Anton deVilliers

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L27/108

Abstract: A self-aligned multiple patterning (SAMP) process is disclosed for formation of structures on substrates. The process provides improved local critical dimension uniformity by using a first (lower) multicolor array pattern and second (upper) multicolor array pattern. The dimensions of finally formed structures are defined by the overlap of a first spacer that is formed as part of the first multicolor array pattern and a second spacer that is formed as part of the second multicolor array pattern. The spacer widths which control the critical dimension of the formed structure may be highly uniform due to the nature of spacer formation and the use of an atomic layer deposition process for forming the spacer layers of the both first (lower) multicolor array pattern and second (upper) multicolor array pattern. In one embodiment, the structure formed by a memory hole pattern for a dynamic random access memory (DRAM).

公开(公告)号：US20200272054A1

公开(公告)日：2020-08-27

申请号：US16680989

申请日：2019-11-12

Applicant: Tokyo Electron Limited

Inventor： Toshiharu Wada ,  Chia-Yun Hsieh ,  Akiteru Ko

IPC: G03F7/20 ,  G03F7/00 ,  G03F7/16 ,  G03F1/22

Abstract: A substrate is provided with a patterned layer, for example, a photo resist layer, which may exhibit line roughness. In one exemplary embodiment, the patterned layer may be an extreme ultraviolet (EUV) photo resist layer. In one method, selective deposition of additional material is provided on the EUV photo resist layer after patterning to provide improved roughness and lithographic structure height to allow for more process margin when transferring the pattern to a layer underlying the photo resist. The additional material is deposited selectively thicker in areas above the photo resist than in areas where the photo resist is not present, such as exposed areas between the photo resist pattern. Pattern transfer to a layer underlying the photo resist may then occur (for example via an etch) while the patterned photo resist and additional material above the photo resist may collectively operate as an etch mask.

公开(公告)号：US20190393084A1

公开(公告)日：2019-12-26

申请号：US16446572

申请日：2019-06-19

Applicant: Tokyo Electron Limited

Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/768 ,  H01L21/311

Abstract: A process is provided in which low-k layers are protected from damage caused by exposure to atmospheric conditions by providing protection through the use of thermal decomposition materials. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. The thermal decomposition materials may be utilized to coat exposed regions of the low-k layers so that the low-k layers are not exposed to atmospheric conditions. In an exemplary embodiment, the low-k layers may be protected by plugging openings in the low-k layer with the thermal decomposition material. In another exemplary embodiment, trench and via openings in the low-k layer are plugged with the thermal decomposition material. The thermal decomposition materials may be removed by a heat based thermal anneal process step that does not damage the low-k layers.

公开(公告)号：US20190385903A1

公开(公告)日：2019-12-19

申请号：US16440679

申请日：2019-06-13

Applicant: Tokyo Electron Limited

Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/324 ,  H01L21/02

Abstract: A process is provided in which low-k layers are protected from damage by the use of thermal decomposition materials. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. The thermal decomposition materials may be utilized to replace organic layers that typically require ashing processes to remove. By removing the need for certain ashing steps, the exposure of the low-k dielectric layer to ashing processes may be lessened. In another embodiment, the low-k layers may be protected by plugging openings in the low-k layer with the thermal decomposition material before a subsequent process step that may damage the low-k layer is performed. The thermal decomposition materials may be removed by a thermal anneal process step that does not damage the low-k layers.

公开(公告)号：US20190189445A1

公开(公告)日：2019-06-20

申请号：US16212144

申请日：2018-12-06

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang Liu ,  Akiteru Ko ,  David L. O'Meara

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/308 ,  H01L21/02 ,  H01L23/00

Abstract: Embodiments are disclosed for processing microelectronic workpieces to apply stress engineering to self-aligned multi-patterning (SAMP) processes. The disclosed processing methods utilize stress in a substrate in a SAMP process to improve resulting pattern parameters. Initially, a high stress film is deposited on the frontside and the backside of the substrate, and the high stress film provides biaxial stress to the substrate due to the deposition process for the high stress film. Next, a SAMP process is performed to form spacers in a spacer pattern. This spacer pattern is then transferred to underlying layers to form a patterned structure. The high stress film provides axial stress in at least one direction along a portion of the patterned structure during the pattern transfer thereby improving resulting pattern formation.

公开(公告)号：US10049875B2

公开(公告)日：2018-08-14

申请号：US15445042

申请日：2017-02-28

Applicant: Tokyo Electron Limited

Inventor： Angelique Raley ,  Akiteru Ko

IPC: H01L21/027 ,  H01L21/66 ,  C23C16/34

Abstract: Provided is a method for critical dimension (CD) trimming of a structure pattern in a substrate, the method comprising: providing a substrate in a process chamber of a patterning system, the substrate comprising a first structure pattern and an underlying layer, the underlying layer comprising a silicon anti-reflective coating (SiARC) or a silicon oxynitride (SiON) layer, an optical planarization layer, and a target patterning layer; performing an optional CD trimming process of the first structure pattern; performing a series of processes to open the SiARC or SiON layer and performing additional CD trimming if required; and performing a series of processes to open the optical planarization layer, the series of processes generating a final structure pattern, and performing additional CD trimming if required; wherein the planarization layer is one of a group comprising an advance patterning film (APF), an organic dielectric layer (ODL) or a spin-on hardmask (SOH) layer.

公开(公告)号：US20180187308A1

公开(公告)日：2018-07-05

申请号：US15906660

申请日：2018-02-27

Applicant: Tokyo Electron Limited

Inventor： Vinh Luong ,  Akiteru Ko

IPC: C23C16/52 ,  C23C16/455 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/033

CPC classification number: C23C16/52 ,  C23C16/45525 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32137 ,  H01L21/32139

Abstract: Provided is a method of forming a spacer sidewall mask, the method comprising: providing a substrate in a process chamber, the substrate having a carbon mandrel pattern and an underlying layer, the underlying layer comprising an amorphous silicon layer above a silicon nitride layer; performing a breakthrough etch process including growth of a conformal native silicon oxide layer, creating an ALD patterned structure; performing a spacer sidewall sculpting process on the ALD patterned structure; performing an amorphous silicon main etch (ME) process on the ALD patterned structure, the ME process causing a spacer oxide open and carbon mandrel removal; and performing an amorphous silicon ME over etch (OE) process on the ALD spacer oxide pattern, the ME OE process transferring the ALD spacer oxide pattern into the amorphous silicon layer, generating a first sculpted pattern comprising a first sculpted sub-structure with a trapezoidal shape.