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    Semiconductor apparatus having stacked devices and method of manufacture thereof
    1.
    发明授权
    Semiconductor apparatus having stacked devices and method of manufacture thereof 有权

    公开(公告)号：US11495540B2

    公开(公告)日：2022-11-08

    申请号：US16660448

    申请日：2019-10-22

    Applicant: Tokyo Electron Limited

    Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers

    IPC: H01L23/528 ,  H01L27/092 ,  H01L21/768 ,  H01L25/07

    Abstract: Aspects of the disclosure provide a semiconductor apparatus including a plurality of structures. A first one of the structures comprises a first stack of transistors that includes a first transistor formed on a substrate and a second transistor stacked on the first transistor along a Z direction substantially perpendicular to a substrate plane of the semiconductor apparatus. The first one of the structures further includes local interconnect structures. The first transistor is sandwiched between two of the local interconnect structures. The first one of the structures further includes vertical conductive structures substantially parallel to the Z direction. The vertical conductive structures are configured to provide at least power supplies for the first one of the structures by electrically coupling with the local interconnect structures. A height of one of the vertical conductive structures along the Z direction is at least a height of the first one of the structures.

    Multiple patterning processes
    2.
    发明授权
    Multiple patterning processes 有权

    公开(公告)号：US11417526B2

    公开(公告)日：2022-08-16

    申请号：US16780248

    申请日：2020-02-03

    Applicant: Tokyo Electron Limited

    Inventor： David L. O'Meara ,  Eric Chih-Fang Liu ,  Jodi Grzeskowiak ,  Anton deVilliers ,  Akiteru Ko ,  Anthony Dip

    IPC: H01L21/033

    Abstract: A method of forming a device includes depositing a first etch mask layer over a mandrel formed using a lithography process. The method includes depositing a second etch mask layer over the first etch mask layer. The method includes, using a first anisotropic etching process, etching the first etch mask layer and the second etch mask layer to form an etch mask including the first etch mask layer and the second etch mask layer. The method includes removing the mandrel to expose an underlying surface of the layer to be patterned. The method includes, using the etch mask, forming a feature by performing a second anisotropic etching process to pattern the layer to be patterned, where during the first anisotropic etching process, the first etch mask layer etches at a first rate and the second etch mask layer etches at a second rate, and where the first rate is different from the second rate.

    Method of liquid filter wetting
    4.
    发明授权
    Method of liquid filter wetting 有权

    公开(公告)号：US10525416B2

    公开(公告)日：2020-01-07

    申请号：US15661551

    申请日：2017-07-27

    Applicant: Tokyo Electron Limited

    Inventor： Hoyoung Kang ,  Anton deVilliers ,  Corey Lemley

    IPC: B01D19/00 ,  B01D65/02 ,  B01D71/36 ,  B01D71/56 ,  B01D63/14 ,  B01D63/06 ,  B01D29/01 ,  B01D29/11 ,  B01D65/00

    Abstract: A process is disclosed for wetting a filter cartridge used to treat a liquid solvent used in semiconductor manufacture. In the process, a filter cartridge having void spaces wherein the void spaces contain residual gas from the manufacturing process used to make the filter cartridge is connected to a source of purging gas. The purging gas is flowed through the filter cartridge to at least partially displace at least a portion of the residual gas from the manufacturing process used to make the filter cartridge. Next, liquid solvent is pumped through the filter cartridge so that the purging gas dissolves into the liquid solvent and to at least partially fill the void spaces to thereby at least partially wet out the filter cartridge with the liquid solvent.

    Three-dimensional semiconductor device including integrated circuit, transistors and transistor components and method of fabrication
    5.
    发明授权
    Three-dimensional semiconductor device including integrated circuit, transistors and transistor components and method of fabrication 有权

    公开(公告)号：US10453850B2

    公开(公告)日：2019-10-22

    申请号：US15654327

    申请日：2017-07-19

    Applicant: TOKYO ELECTRON LIMITED

    Inventor： Jeffrey Smith ,  Anton deVilliers

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/06 ,  H01L27/11 ,  H01L29/423

    Abstract: A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space. A conductive fill material is provided in the electrode space, and a dielectric layer electrically separates the conductive fill material into a first electrode electrically connected to the first contact of the first semiconductor device and a second electrode electrically connected to the second semiconductor device and electrically insulated from the first electrode. A first circuit terminal extends vertically from the top or bottom surface of the electrode structure and is electrically connected to the first electrode.

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
    7.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION 审中-公开

    公开(公告)号：US20180240802A1

    公开(公告)日：2018-08-23

    申请号：US15963766

    申请日：2018-04-26

    Applicant: TOKYO ELECTRON LIMITED

    Inventor： Jeffrey SMITH ,  Anton deVilliers

    IPC: H01L27/11 ,  H01L27/06

    Abstract: A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space. A conductive fill material is provided in the electrode space, and a dielectric layer electrically separates the conductive fill material into a first electrode electrically connected to the first contact of the first semiconductor device and a second electrode electrically connected to the second semiconductor device and electrically insulated from the first electrode. A first circuit terminal extends vertically from the top or bottom surface of the electrode structure and is electrically connected to the first electrode.

    Compact 3D stacked-CFET architecture for complex logic cells
    9.
    发明授权
    Compact 3D stacked-CFET architecture for complex logic cells 有权

    公开(公告)号：US11437376B2

    公开(公告)日：2022-09-06

    申请号：US16849630

    申请日：2020-04-15

    Applicant: Tokyo Electron Limited

    Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers ,  Daniel Chanemougame

    IPC: H01L27/092 ,  H01L29/08 ,  H01L23/535 ,  H01L23/528 ,  H03K19/21

    Abstract: A 3D IC includes a substrate having a substrate surface, a first stack of semiconductor devices stacked along a thickness direction of the substrate, and a second stack of semiconductor devices stacked along the thickness direction of the substrate and provided adjacent to the first stack in a direction along the substrate surface. Each semiconductor device of the first and second stack includes a gate and a pair of source-drain regions provided on opposite sides of the respective gate, and each gate of the first and second stack is a split gate. A gate contact is physically connected to a first split gate of a first one of the semiconductor devices. The gate contact forms at least part of a local interconnect structure that electrically connects the first semiconductor device to a second semiconductor device in the 3D IC.

    Method and process for forming memory hole patterns
    10.
    发明授权
    Method and process for forming memory hole patterns 有权

    公开(公告)号：US11049721B2

    公开(公告)日：2021-06-29

    申请号：US16561350

    申请日：2019-09-05

    Applicant: Tokyo Electron Limited

    Inventor： Toshiharu Wada ,  Akiteru Ko ,  Anton deVilliers

    IPC: H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L27/108

    Abstract: A self-aligned multiple patterning (SAMP) process is disclosed for formation of structures on substrates. The process provides improved local critical dimension uniformity by using a first (lower) multicolor array pattern and second (upper) multicolor array pattern. The dimensions of finally formed structures are defined by the overlap of a first spacer that is formed as part of the first multicolor array pattern and a second spacer that is formed as part of the second multicolor array pattern. The spacer widths which control the critical dimension of the formed structure may be highly uniform due to the nature of spacer formation and the use of an atomic layer deposition process for forming the spacer layers of the both first (lower) multicolor array pattern and second (upper) multicolor array pattern. In one embodiment, the structure formed by a memory hole pattern for a dynamic random access memory (DRAM).

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