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    Method for filling recessed features in semiconductor devices with a low-resistivity metal
    23.
    发明授权
    Method for filling recessed features in semiconductor devices with a low-resistivity metal 有权

    公开(公告)号：US11024535B2

    公开(公告)日：2021-06-01

    申请号：US16598772

    申请日：2019-10-10

    Applicant: Tokyo Electron Limited

    Inventor： Kai-Hung Yu ,  David O'Meara ,  Nicholas Joy ,  Gyanaranjan Pattanaik ,  Robert Clark ,  Kandabara Tapily ,  Takahiro Hakamata ,  Cory Wajda ,  Gerrit Leusink

    IPC: H01L21/768

    Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.

    Interconnect structure and method of forming the same
    24.
    发明授权
    Interconnect structure and method of forming the same 有权

    公开(公告)号：US10923392B2

    公开(公告)日：2021-02-16

    申请号：US16562207

    申请日：2019-09-05

    Applicant: Tokyo Electron Limited

    Inventor： Soo Doo Chae ,  Jeffrey Smith ,  Gerrit J. Leusink ,  Robert D. Clark ,  Kai-Hung Yu

    IPC: H01L21/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/285

    Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.

    METHOD FOR USING ULTRA THIN RUTHENIUM METAL HARD MASK FOR ETCHING PROFILE CONTROL
    25.
    发明申请
    METHOD FOR USING ULTRA THIN RUTHENIUM METAL HARD MASK FOR ETCHING PROFILE CONTROL 有权

    公开(公告)号：US20210028017A1

    公开(公告)日：2021-01-28

    申请号：US16582297

    申请日：2019-09-25

    Applicant: Tokyo Electron Limited

    Inventor： Yen-Tien Lu ,  Kai-Hung Yu ,  Angelique Raley

    IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/311

    Abstract: A method of processing substrates, in one example microelectronic workpieces, is disclosed that includes forming a multi-layer metal hard mask (MHM) layer in which at least one lower layer of the multi-layer MHM is comprised of ruthenium (Ru). The Ru MHM layer may be an atomic layer deposition (ALD) Ru MHM layer formed over one or more underlying layers on a substrate. The ALD Ru MHM layer may be etched to provide a patterned ALD Ru MHM layer, and then the one or more underlying layers may be etched using, at least in part, the patterned ALD Ru MHM layer as a mask to protect portion of the one or more underlying layers. In one embodiment, at least one of the underlying layers is a hard mask layer.

    Method of integrated circuit fabrication with dual metal power rail
    27.
    发明授权
    Method of integrated circuit fabrication with dual metal power rail 有权

    公开(公告)号：US10580691B2

    公开(公告)日：2020-03-03

    申请号：US16001695

    申请日：2018-06-06

    Applicant: Tokyo Electron Limited

    Inventor： Soo Doo Chae ,  Kaoru Maekawa ,  Jeffrey Smith ,  Nicholas Joy ,  Gerrit J. Leusink ,  Kai-Hung Yu

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

    Abstract: A substrate processing method is provided for metal filling of recessed features in a substrate. According to one embodiment, the method includes providing a substrate containing horizontally spaced nested and isolated recessed features, filling the nested and isolated recessed features with a blocking material, and performing in any order: a) sequentially first, removing the blocking material from the nested recessed features, and second, filling the nested recessed features with a first metal, and b) sequentially first, removing the blocking material from the isolated recessed features, and second, filling the isolated recessed features with a second metal that is different from the first metal. According to one embodiment, the first metal may include Ru metal and the second metal may include Cu metal. According to one embodiment, a microelectronic device containing metal filled recessed features is provided.

    Removal method and processing method
    28.
    发明授权
    Removal method and processing method 有权

    公开(公告)号：US10460988B2

    公开(公告)日：2019-10-29

    申请号：US15850458

    申请日：2017-12-21

    Applicant: Tokyo Electron Limited

    Inventor： Takeshi Itatani ,  Tadahiro Ishizaka ,  Kandabara Tapily ,  Kai-Hung Yu ,  Wanjae Park

    IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/687

    Abstract: A removal method is provided for selectively removing a plurality of types of metal oxide films in a plurality of recesses formed in a substrate that is arranged in a processing chamber. The removal method includes repeatedly performing process steps of exposing the plurality of types of metal oxide films to BCl3 gas or a BCl3 gas plasma generated by introducing BCl3 gas, stopping introduction of the BCl3 gas and performing a purge process, exposing the plurality of types of metal oxide films and/or a plurality of types of metal films underneath the metal oxide films to one or more different plasmas, at least one of which is generated by introducing a single gas of an inert gas, and stopping introduction of the inert gas and performing the purge process.

    PLATFORM AND METHOD OF OPERATING FOR INTEGRATED END-TO-END CMP-LESS INTERCONNECT PROCESS
    29.
    发明申请
    PLATFORM AND METHOD OF OPERATING FOR INTEGRATED END-TO-END CMP-LESS INTERCONNECT PROCESS 审中-公开

    公开(公告)号：US20190295887A1

    公开(公告)日：2019-09-26

    申请号：US16356272

    申请日：2019-03-18

    Applicant: Tokyo Electron Limited

    Inventor： Ying Trickett ,  Kai-Hung Yu ,  Nicholas Joy ,  Kaoru Maekawa ,  Robert Clark

    IPC: H01L21/768 ,  H01L21/67 ,  H01L21/677 ,  H01L21/66

    Abstract: A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules is provided. A workpiece having an upper planar surface is received into the common manufacturing platform. The method further includes conformally applying a thin film over the feature pattern using one of the film-forming modules, removing the thin film from upper surfaces of the feature pattern using one of the etching modules to leave behind the thin film in the recessed feature, and removing the fill material from the upper planar surface of the workpiece. The integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment.

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