公开(公告)号：US20250105059A1

公开(公告)日：2025-03-27

申请号：US18471823

申请日：2023-09-21

Applicant: Tokyo Electron Limited

Inventor： Ryota Yonezawa ,  Kai-Hung Yu ,  Ying Trickett ,  Hidenao Suzuki

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532

Abstract: A method of processing a substrate includes exposing the substrate to a boron-containing precursor to adsorb over the substrate, where the substrate includes a dielectric layer formed over a conductive layer, and the conductive layer is exposed at a bottom of a recess formed in the dielectric layer. The method includes exposing the adsorbed boron-containing precursor to a plasma and filling the recess with a conductive fill material bottom up by a vapor deposition process, where a vertical deposition rate of the conductive fill material is greater than a lateral deposition rate of the conductive fill material.

公开(公告)号：US20170125517A1

公开(公告)日：2017-05-04

申请号：US15342968

申请日：2016-11-03

Applicant: Tokyo Electron Limited

Inventor： Kandabara N. Tapily ,  Ying Trickett ,  Chihiro Tamura ,  Cory Wajda ,  Gerrit J. Leusink ,  Kaoru Maekawa

IPC: H01L29/06 ,  H01L21/311 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/0673 ,  H01J37/32192 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/16 ,  H01L29/775

Abstract: Embodiments of the invention describe a method of corner rounding and trimming of nanowires used in semiconductor devices. According to one embodiment, the method includes providing in a process chamber a plurality of nanowires separated from each other by a void, where the plurality of nanowires have a height and at least substantially right angle corners, forming an oxidized surface layer on the plurality of nanowires using an oxidizing microwave plasma, removing the oxidized surface layer to trim the height and round the corners of the plurality of nanowires, and repeating the forming and removing at least once until the plurality of nanowires have a desired trimmed height and rounded corners.

公开(公告)号：US12237216B2

公开(公告)日：2025-02-25

申请号：US17688343

申请日：2022-03-07

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Shihsheng Chang ,  Ying Trickett ,  Eric Chih-Fang Liu ,  Yun Han ,  Henan Zhang ,  Cory Wajda ,  Robert D. Clark ,  Gerrit J. Leusink ,  Gyanaranjan Pattanaik ,  Hiroaki Niimi

IPC: H01L21/768

Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.

公开(公告)号：US10861744B2

公开(公告)日：2020-12-08

申请号：US16356272

申请日：2019-03-18

Applicant: Tokyo Electron Limited

Inventor： Ying Trickett ,  Kai-Hung Yu ,  Nicholas Joy ,  Kaoru Maekawa ,  Robert Clark

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/67 ,  H01L21/66 ,  H01L21/677 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  G05B13/02 ,  G05B19/418 ,  C23C14/24 ,  C23C14/34 ,  H01J37/32

Abstract: A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules is provided. A workpiece having an upper planar surface is received into the common manufacturing platform. The method further includes conformally applying a thin film over the feature pattern using one of the film-forming modules, removing the thin film from upper surfaces of the feature pattern using one of the etching modules to leave behind the thin film in the recessed feature, and removing the fill material from the upper planar surface of the workpiece. The integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment.

公开(公告)号：US20190295887A1

公开(公告)日：2019-09-26

申请号：US16356272

申请日：2019-03-18

Applicant: Tokyo Electron Limited

Inventor： Ying Trickett ,  Kai-Hung Yu ,  Nicholas Joy ,  Kaoru Maekawa ,  Robert Clark

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/677 ,  H01L21/66

Abstract: A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules is provided. A workpiece having an upper planar surface is received into the common manufacturing platform. The method further includes conformally applying a thin film over the feature pattern using one of the film-forming modules, removing the thin film from upper surfaces of the feature pattern using one of the etching modules to leave behind the thin film in the recessed feature, and removing the fill material from the upper planar surface of the workpiece. The integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment.

公开(公告)号：US20220301930A1

公开(公告)日：2022-09-22

申请号：US17688343

申请日：2022-03-07

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Shihsheng Chang ,  Ying Trickett ,  Eric Chih-Fang Liu ,  Yun Han ,  Henan Zhang ,  Cory Wajda ,  Robert D. Clark ,  Gerrit J. Leusink ,  Gyanaranjan Pattanaik ,  Hiroaki Niimi

IPC: H01L21/768

Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.

公开(公告)号：US10008564B2

公开(公告)日：2018-06-26

申请号：US15342968

申请日：2016-11-03

Applicant: Tokyo Electron Limited

Inventor： Kandabara N. Tapily ,  Ying Trickett ,  Chihiro Tamura ,  Cory Wajda ,  Gerrit J. Leusink ,  Kaoru Maekawa

IPC: H01L21/311 ,  H01L21/30 ,  H01L21/46 ,  H01L29/06 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/0673 ,  H01J37/32192 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/16 ,  H01L29/775

Abstract: Embodiments of the invention describe a method of corner rounding and trimming of nanowires used in semiconductor devices. According to one embodiment, the method includes providing in a process chamber a plurality of nanowires separated from each other by a void, where the plurality of nanowires have a height and at least substantially right angle corners, forming an oxidized surface layer on the plurality of nanowires using an oxidizing microwave plasma, removing the oxidized surface layer to trim the height and round the corners of the plurality of nanowires, and repeating the forming and removing at least once until the plurality of nanowires have a desired trimmed height and rounded corners.