公开(公告)号：US20170154823A1

公开(公告)日：2017-06-01

申请号：US14981929

申请日：2015-12-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L27/088 ,  H01L21/311

CPC classification number: H01L21/823481 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a first shallow trench isolation (STI) around the fin-shaped structure; dividing the fin-shaped structure into a first portion and a second portion; and forming a second STI between the first portion and the second portion.

公开(公告)号：US09466691B2

公开(公告)日：2016-10-11

申请号：US14541107

申请日：2014-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Rai-Min Huang ,  Tong-Jyun Huang ,  Kuan-Hsien Li ,  Chen-Ming Huang

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L29/66537 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin shaped structure and a method of forming the same, wherein the method includes forming a fin structure on a substrate. Next, an insulation layer is formed on the substrate and surrounds the fin structure, wherein the insulation layer covers a bottom portion of the fin structure to expose an exposed portion of the fin structure protruded from the insulation layer. Then, a buffer layer is formed on the fin structure. Following this, a threshold voltage implantation process is performed to penetrate through the buffer layer after forming the insulation layer, to form a first doped region on the exposed portion of the fin structure.

Abstract translation: 鳍状结构及其形成方法，其中，所述方法包括在基板上形成翅片结构。 接下来，在衬底上形成绝缘层并围绕鳍结构，其中绝缘层覆盖翅片结构的底部以暴露从绝缘层突出的鳍结构的暴露部分。 然后，在翅片结构上形成缓冲层。 接下来，在形成绝缘层之后，执行阈值电压注入工艺以穿透缓冲层，以在鳍结构的暴露部分上形成第一掺杂区域。

公开(公告)号：US20160141387A1

公开(公告)日：2016-05-19

申请号：US14541107

申请日：2014-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Rai-Min Huang ,  Tong-Jyun Huang ,  Kuan-Hsien Li ,  Chen-Ming Huang

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L21/308 ,  H01L29/10 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66537 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin shaped structure and a method of forming the same, wherein the method includes forming a fin structure on a substrate. Next, an insulation layer is formed on the substrate and surrounds the fin structure, wherein the insulation layer covers a bottom portion of the fin structure to expose an exposed portion of the fin structure protruded from the insulation layer. Then, a buffer layer is formed on the fin structure. Following this, a threshold voltage implantation process is performed to penetrate through the buffer layer after forming the insulation layer, to form a first doped region on the exposed portion of the fin structure.

Abstract translation: 鳍状结构及其形成方法，其中，所述方法包括在基板上形成翅片结构。 接下来，在衬底上形成绝缘层并围绕鳍结构，其中绝缘层覆盖翅片结构的底部以暴露从绝缘层突出的鳍结构的暴露部分。 然后，在翅片结构上形成缓冲层。 接下来，在形成绝缘层之后，执行阈值电压注入工艺以穿透缓冲层，以在鳍结构的暴露部分上形成第一掺杂区域。

公开(公告)号：US20160099179A1

公开(公告)日：2016-04-07

申请号：US14506009

申请日：2014-10-03

Applicant: United Microelectronics Corp.

Inventor： Chun-Tsen Lu ,  Chih-Jung Su ,  Jian-Wei Chen ,  Shui-Yen Lu ,  Yi-Wen Chen ,  Po-Cheng Huang ,  Chen-Ming Huang ,  Shih-Fang Tzou

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L21/3105

CPC classification number: H01L29/66545 ,  H01L21/0206 ,  H01L21/02065 ,  H01L21/02271 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/4966 ,  H01L29/517

Abstract: A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed.

Abstract translation: 公开了一种形成半导体器件的方法。 提供具有多个翅片的基板。 绝缘层填充两个相邻翅片之间的间隙的下部。 在一个翅片上形成至少一个第一堆叠结构，并且在一个绝缘层上形成至少一个第二堆叠结构。 形成第一电介质层以覆盖第一和第二堆叠结构。 去除第一电介质层的一部分和第一和第二堆叠结构的部分。 去除第一电介质层的另一部分，直到剩余的第一电介质层的顶部低于第一和第二堆叠结构的顶部。 形成第二电介质层以覆盖第一和第二堆叠结构。 去除第二电介质层的一部分直到第一和第二堆叠结构的顶部露出。

公开(公告)号：US20240282637A1

公开(公告)日：2024-08-22

申请号：US18613151

申请日：2024-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/764 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

公开(公告)号：US11972984B2

公开(公告)日：2024-04-30

申请号：US18088631

申请日：2022-12-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/764 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

公开(公告)号：US09859147B2

公开(公告)日：2018-01-02

申请号：US15336811

申请日：2016-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tong-Jyun Huang ,  Rai-Min Huang ,  I-Ming Tseng ,  Kuan-Hsien Li ,  Chen-Ming Huang

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/02 ,  H01L27/088 ,  H01L21/3065

CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.

公开(公告)号：US09607985B1

公开(公告)日：2017-03-28

申请号：US14864908

申请日：2015-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L21/70 ,  H01L27/088 ,  H01L29/06 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/3081 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a plurality of fin shaped structures, a first trench and at least one bump. The substrate has a base. The fin shaped structures protrude from the base of the substrate. The first trench recesses from the base of the substrate and has a depth being smaller than a width of each of the fin shaped structures. The at least one bump is disposed on a surface of the first trench.

公开(公告)号：US20170040435A1

公开(公告)日：2017-02-09

申请号：US14840041

申请日：2015-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Tsen Lu ,  Chien-Ming Lai ,  Lu-Sheng Chou ,  Ya-Huei Tsai ,  Ching-Hsiang Chiu ,  Yu-Tung Hsiao ,  Chen-Ming Huang ,  Kun-Ju Li ,  Yu-Ping Wang

IPC: H01L29/66 ,  H01L29/49 ,  C22C32/00 ,  H01L29/423

CPC classification number: H01L29/66545 ,  B32B1/00 ,  B32B18/00 ,  C22C32/0068 ,  H01L21/28088 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/511

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.

Abstract translation: 公开了一种半导体器件。 半导体器件包括衬底和衬底上的栅极结构。 栅极结构包括在衬底上的高k电介质层和高k电介质层上的底部阻挡金属（BBM）层。 优选地，BBM层包括顶部，中间部分和底部，其中顶部是富氮部分，中部和底部是富钛部分。

公开(公告)号：US20170012000A1

公开(公告)日：2017-01-12

申请号：US14844004

申请日：2015-09-03

Applicant: United Microelectronics Corp.

Inventor： I-Ming Tseng ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L23/535 ,  H01L29/16 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823475 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7851

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device including a fin structure, a first liner, a first insulating layer and a dummy gate structure. The fin structure is disposed on a substrate, where the fin structure has a trench. The first liner disposed in the trench. The first insulating layer disposed on the first liner. The dummy gate structure is disposed on the first insulating layer and disposed above the trench, where a bottom surface of the dummy gate and a top surface of the fin structure are on a same level.

Abstract translation: 一种半导体器件及其制造方法，所述半导体器件包括翅片结构，第一衬垫，第一绝缘层和虚拟栅极结构。 翅片结构设置在基板上，其中鳍结构具有沟槽。 布置在沟槽中的第一个衬垫。 第一绝缘层设置在第一衬垫上。 虚拟栅极结构设置在第一绝缘层上并且设置在沟槽上方，其中虚拟栅极的底表面和鳍状结构的顶表面处于同一水平面上。