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    Magnetic random access memory structure
    22.
    发明申请
    Magnetic random access memory structure 有权

    公开(公告)号：US20220406994A1

    公开(公告)日：2022-12-22

    申请号：US17376179

    申请日：2021-07-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Da-Jun Lin ,  Ching-Hua Hsu ,  Fu-Yu Tsai ,  Bin-Siang Tsai

    IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

    Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a dielectric layer, a plurality of MTJ stacked elements and at least one dummy MTJ stacked element located in the dielectric layer, a first nitride layer covering at least the sidewalls of the MTJ stacked elements and the dummy MTJ stacked elements, a second nitride layer covering the top surfaces of the dummy MTJ stacked elements, the thickness of the second nitride layer is greater than the thickness of the first nitride layer, and a plurality of contact structures located in the dielectric layer and electrically connected with each MTJ stacked element.

    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF
    24.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20220310697A1

    公开(公告)日：2022-09-29

    申请号：US17228720

    申请日：2021-04-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Ching-Hua Hsu ,  Chen-Yi Weng ,  Po-Kai Hsu

    IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

    Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.

    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE
    26.
    发明申请
    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20250169368A1

    公开(公告)日：2025-05-22

    申请号：US18407360

    申请日：2024-01-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chau-Chung Hou ,  Kun-Ju Li ,  Hsin-Jung Liu ,  Ching-Hua Hsu ,  Chen-Yi Weng ,  Chih-Yueh Li ,  Hsin-Kuo Hsu ,  Ying-Chu Chen ,  Yi-Chen Hsiao

    IPC: H10N50/01 ,  G11C11/16 ,  H10B61/00 ,  H10N50/80

    Abstract: A method of forming a semiconductor structure is disclosed. A substrate is provided having a memory array area and a peripheral region. A memory structure is formed on the substrate in the memory array area. A step height is formed between the memory array area and the peripheral region. A dielectric layer is deposited. The dielectric layer covers the memory structure. A reverse etching process is performed to remove part of the dielectric layer from the memory array area, thereby forming an upwardly protruding wall structure along the perimeter of the memory array area, wherein the thickness of the dielectric layer in the memory array area increases from the central area of the memory array area to the periphery of the memory array area. A polishing process is performed on the dielectric layer to remove the upwardly protruding wall structure from the memory array area.

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