公开(公告)号：US20170069543A1

公开(公告)日：2017-03-09

申请号：US14884746

申请日：2015-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Chien-Ting Lin ,  Yi-Ren Chen ,  Shou-Wei Hsieh ,  Hsin-Yu Chen ,  Chun-Hao Lin

IPC: H01L21/8238 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/02129 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有鳍状结构的衬底和围绕鳍状结构的浅沟槽隔离（STI），其中鳍状结构具有顶部和底部; 在STI和顶部上形成第一掺杂层; 并执行第一退火处理。

公开(公告)号：US20160351712A1

公开(公告)日：2016-12-01

申请号：US14754708

申请日：2015-06-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hsin-Yu Chen ,  Hao-Ming Lee

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/3105 ,  H01L29/49 ,  H01L21/324 ,  H01L21/28 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an interlayer dielectric (ILD) layer around the gate structure; removing the gate structure to form a recess; forming a stress layer in the recess, wherein the stress layer comprises metal; and forming a work function layer on the stress layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在基板上形成栅极结构; 在所述栅极结构周围形成层间电介质（ILD）层; 移除所述门结构以形成凹部; 在所述凹部中形成应力层，其中所述应力层包括金属; 并在应力层上形成功函数层。

公开(公告)号：US09431482B2

公开(公告)日：2016-08-30

申请号：US14614392

申请日：2015-02-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Sheng-Hao Lin ,  Huai-Tzu Chiang ,  Hao-Ming Lee

IPC: H01L29/06 ,  H01L21/32 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L29/10

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/3247 ,  H01L29/0669 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides some methods for forming at least two different nanowire structures with different diameters on one substrate. Since the diameter of the nanowire structure will influence the threshold voltage (Vt) and the drive currents of a nanowire field effect transistor, in this invention, at least two nanowire structures with different diameters can be formed on one substrate. Therefore, in the following steps, these nanowire structures can be applied in different nanowire field effect transistors with different Vt and drive currents. This way, the flexibility of the nanowire field effect transistors can be improved.

Abstract translation: 本发明提供了在一个基底上形成具有不同直径的至少两种不同纳米线结构的一些方法。 由于纳米线结构的直径将影响纳米线场效应晶体管的阈值电压（Vt）和驱动电流，所以在本发明中，可以在一个衬底上形成具有不同直径的至少两个纳米线结构。 因此，在以下步骤中，这些纳米线结构可以应用于具有不同Vt和驱动电流的不同纳米线场效应晶体管中。 这样，可以提高纳米线场效应晶体管的灵活性。

公开(公告)号：US20160225850A1

公开(公告)日：2016-08-04

申请号：US14614392

申请日：2015-02-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Sheng-Hao Lin ,  Huai-Tzu Chiang ,  Hao-Ming Lee

IPC: H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L21/324 ,  H01L21/306

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/3247 ,  H01L29/0669 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides some methods for forming at least two different nanowire structures with different diameters on one substrate. Since the diameter of the nanowire structure will influence the threshold voltage (Vt) and the drive currents of a nanowire field effect transistor, in this invention, at least two nanowire structures with different diameters can be formed on one substrate. Therefore, in the following steps, these nanowire structures can be applied in different nanowire field effect transistors with different Vt and drive currents. This way, the flexibility of the nanowire field effect transistors can be improved.

Abstract translation: 本发明提供了在一个基底上形成具有不同直径的至少两种不同纳米线结构的一些方法。 由于纳米线结构的直径将影响纳米线场效应晶体管的阈值电压（Vt）和驱动电流，所以在本发明中，可以在一个衬底上形成具有不同直径的至少两个纳米线结构。 因此，在以下步骤中，这些纳米线结构可以应用于具有不同Vt和驱动电流的不同纳米线场效应晶体管中。 这样，可以提高纳米线场效应晶体管的灵活性。

公开(公告)号：US09312208B2

公开(公告)日：2016-04-12

申请号：US14521456

申请日：2014-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Home-Been Cheng ,  Yu-Han Tsai ,  Ching-Li Yang

IPC: H01L21/44 ,  H01L23/48 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/481 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via.

公开(公告)号：US12249649B2

公开(公告)日：2025-03-11

申请号：US17207751

申请日：2021-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Shou-Wei Hsieh ,  Chih-Ming Su ,  Yi-Ren Chen ,  Yuan-Ting Chuang

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/417

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

公开(公告)号：US12125900B2

公开(公告)日：2024-10-22

申请号：US17983417

申请日：2022-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66628 ,  H01L21/76232 ,  H01L29/6656 ,  H01L29/66787

Abstract: A semiconductor device includes a gate structure on a substrate, a single diffusion break (SDB) structure adjacent to the gate structure, a first spacer adjacent to the gate structure, a second spacer adjacent to the SDB structure, a source/drain region between the first spacer and the second spacer, an interlayer dielectric (ILD) layer around the gate structure and the SDB structure, and a contact plug in the ILD layer and on the source/drain region. Preferably, a top surface of the second spacer is lower than a top surface of the first spacer.

公开(公告)号：US12100750B2

公开(公告)日：2024-09-24

申请号：US18093330

申请日：2023-01-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66628 ,  H01L21/76232 ,  H01L29/6656 ,  H01L29/66787

Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

公开(公告)号：US10991824B2

公开(公告)日：2021-04-27

申请号：US16252715

申请日：2019-01-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Han Wu ,  Hsin-Yu Chen ,  Chun-Hao Lin ,  Shou-Wei Hsieh ,  Chih-Ming Su ,  Yi-Ren Chen ,  Yuan-Ting Chuang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/417

Abstract: A semiconductor device includes: a fin-shaped structure on the substrate; a shallow trench isolation (STI) around the fin-shaped structure; a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure; a second gate structure on the STI; and a third gate structure on the SDB structure, wherein a width of the third gate structure is greater than a width of the second gate structure.

公开(公告)号：US10483395B2

公开(公告)日：2019-11-19

申请号：US15849599

申请日：2017-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/027 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first buffer layer on the first fin-shaped structure and the second fin-shaped structure; removing the first buffer layer on the first region; and performing a curing process so that a width of the first fin-shaped structure is different from a width of the second fin-shaped structure.