公开(公告)号：US09190497B2

公开(公告)日：2015-11-17

申请号：US14630666

申请日：2015-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Hong ,  Po-Chao Tsao

IPC: H01L29/66 ,  H01L27/088

CPC classification number: H01L29/66795 ,  H01L27/0886 ,  H01L29/6653

Abstract: A fabrication method of a semiconductor device includes the following steps. First, sacrificial patterns are formed on a substrate and a space is formed on the sidewalls of each sacrificial pattern. Then, the sacrificial patterns are removed and patterns of the spacers are transferred into the substrate to form a fin structure. The fin structure includes a horizontal fin structure extending along a first direction and a vertical fin structure extending along a second direction. Subsequently, a gate structure, source/drain structures, and an electrical connecting structure are formed sequentially on the substrate. The gate structure overlaps portions of the horizontal fin structure. The source/drain structures are respectively on each side of the gate structure. The electrical connecting structure directly covers the horizontal fin structure and the vertical fin structure.

Abstract translation: 半导体器件的制造方法包括以下步骤。 首先，牺牲图案形成在基板上，并且在每个牺牲图案的侧壁上形成空间。 然后，去除牺牲图案，并将间隔物的图案转移到基板中以形成翅片结构。 翅片结构包括沿着第一方向延伸的水平翅片结构和沿着第二方向延伸的垂直翅片结构。 随后，在衬底上依次形成栅极结构，源极/漏极结构和电连接结构。 门结构与水平翅片结构的部分重叠。 源极/漏极结构分别位于栅极结构的每一侧。 电连接结构直接覆盖水平翅片结构和垂直翅片结构。

公开(公告)号：US20150052491A1

公开(公告)日：2015-02-19

申请号：US13968391

申请日：2013-08-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Shih-Fang Hong ,  Chia-Wei Huang ,  Ming-Jui Chen ,  Shih-Fang Tzou ,  Ming-Te Wei

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G03F1/144 ,  G03F1/36

Abstract: A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns.

Abstract translation: 提供了一种用于生成布局图案的方法。 首先，将布局图案提供给计算机系统，并将其分为两个子图案和空白图案。 每个子图案具有简单整数比例的间距，并且空白图案在两个子图案之间。 然后，生成多个第一条纹图案和至少两个第二条纹图案。 第一条形图案的边缘与子图案的边缘对齐，并且第一条纹图案具有相等的间隔和宽度。 第二条纹图案的间距或宽度与第一条纹图案的间距或宽度不同。

公开(公告)号：US20140339641A1

公开(公告)日：2014-11-20

申请号：US13895367

申请日：2013-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Hong ,  Po-Chao Tsao

IPC: H01L27/088

CPC classification number: H01L29/66795 ,  H01L27/0886 ,  H01L29/6653

Abstract: A semiconductor device includes a substrate, a first fin structure, an electrical contact structure and a gate structure. The first fin structure includes a horizontal fin structure extending along a first direction and a vertical fin structure extending along a second direction. The substrate has a first region and a second region. A portion of the horizontal fin structure and the vertical fin structure are disposed in the first region, and the electrical contact structure directly covers the horizontal fin structure and the vertical fin structure within the first region. The gate structure partially overlaps the horizontal fin structure within the second region.

Abstract translation: 半导体器件包括衬底，第一鳍结构，电接触结构和栅极结构。 第一翅片结构包括沿着第一方向延伸的水平翅片结构和沿着第二方向延伸的垂直翅片结构。 衬底具有第一区域和第二区域。 水平翅片结构和垂直翅片结构的一部分设置在第一区域中，并且电接触结构直接覆盖第一区域内的水平翅片结构和垂直翅片结构。 栅极结构部分地与第二区域内的水平翅片结构重叠。

公开(公告)号：US09954108B2

公开(公告)日：2018-04-24

申请号：US15458035

申请日：2017-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yi Chiu ,  Shih-Fang Hong ,  Chao-Hung Lin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure includes a top portion which protrudes from a bottom surface of the fin shaped structure and the fin shaped structure is directly disposed on the silicon substrate. The bottom surface of the fin shaped structure covers an entire top surface of the silicon substrate. The fin shaped structure further includes a silicon germanium (SiGe) layer extending within the fin shaped structure and occupying the whole top portion of the shaped structure. The fin shaped structure is a semiconductor fin shaped structure, and the material of the silicon substrate is different from the material of the silicon germanium layer The shallow trench isolation is disposed on the top portion and the bottom surface of the fin shaped structure.

公开(公告)号：US09859148B2

公开(公告)日：2018-01-02

申请号：US15610574

申请日：2017-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Shih-Fang Hong ,  Jyh-Shyang Jenq

IPC: H01L21/00 ,  H01L21/762 ,  H01L27/11 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/76229 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a plurality of spacers on the first region, the second region, and the third region; forming a first patterned mask to cover the spacers on the first region and the second region; and removing the spacers on the third region.

公开(公告)号：US09704737B2

公开(公告)日：2017-07-11

申请号：US14816081

申请日：2015-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Shih-Fang Hong ,  Jyh-Shyang Jenq

IPC: H01L21/00 ,  H01L21/762 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/76229 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a plurality of spacers on the first region, the second region, and the third region; forming a first patterned mask to cover the spacers on the first region and the second region; and removing the spacers on the third region.

公开(公告)号：US20170186872A1

公开(公告)日：2017-06-29

申请号：US15458035

申请日：2017-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yi Chiu ,  Shih-Fang Hong ,  Chao-Hung Lin

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure includes a top portion which protrudes from a bottom surface of the fin shaped structure and the fin shaped structure is directly disposed on the silicon substrate. The bottom surface of the fin shaped structure covers an entire top surface of the silicon substrate. The fin shaped structure further includes a silicon germanium (SiGe) layer extending within the fin shaped structure and occupying the whole top portion of the shaped structure. The fin shaped structure is a semiconductor fin shaped structure, and the material of the silicon substrate is different from the material of the silicon germanium layer The shallow trench isolation is disposed on the top portion and the bottom surface of the fin shaped structure.

公开(公告)号：US09559164B2

公开(公告)日：2017-01-31

申请号：US14634904

申请日：2015-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Shih-Fang Hong ,  Chao-Hung Lin ,  Jyh-Shyang Jenq

IPC: H01L27/12 ,  H01L21/20 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L21/02603 ,  H01L21/823807 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: A nanowire transistor device includes a substrate, a plurality of nanowires formed on the substrate, and a gate surrounding at least a portion of each nanowire. The nanowires respectively include a first semiconductor core and a second semiconductor core surrounding the first semiconductor core. A lattice constant of the second semiconductor core is different from a lattice constant of the first semiconductor core.

Abstract translation: 纳米线晶体管器件包括衬底，形成在衬底上的多个纳米线和围绕每个纳米线的至少一部分的栅极。 纳米线分别包括第一半导体芯和围绕第一半导体芯的第二半导体芯。 第二半导体芯的晶格常数与第一半导体芯的晶格常数不同。

公开(公告)号：US09530646B2

公开(公告)日：2016-12-27

申请号：US14629491

申请日：2015-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Hon-Huei Liu ,  An-Chi Liu ,  Chih-Wei Wu ,  Jyh-Shyang Jenq ,  Shih-Fang Hong ,  En-Chiuan Liou ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chih-Kai Hsu ,  Mei-Chen Chen ,  Chia-Hsun Tseng

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/66 ,  H01L21/308

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L22/12

Abstract: A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.

Abstract translation: 形成半导体结构的方法包括以下步骤。 首先，提供具有多个心轴图案的图案化的硬掩模层。 接下来，通过图案化的硬掩模在基板上形成多个第一心轴。 接下来，执行至少一个侧壁图像传送（SIT）处理。 最后，在基板上形成多个散热片，其中每个翅片具有预定的临界尺寸（CD），并且每个心轴图案具有比预定CD大5-8倍的CD。

公开(公告)号：US09349695B2

公开(公告)日：2016-05-24

申请号：US14803128

申请日：2015-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Hong ,  Po-Chao Tsao

IPC: H01L29/78 ,  H01L23/00 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L21/84 ,  H01L27/092 ,  H01L27/108 ,  H01L29/423 ,  H01L27/088 ,  H01L27/12

CPC classification number: H01L23/562 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0692 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor integrated device includes a substrate having an active region defined thereon, a plurality of active fins positioned in the active region, and a plurality of first protecting fins surrounding the active region. Each of the plurality of active fins extends along a first direction and includes a first length along the first direction. The plurality of first protecting fins extend along the first direction. One of the plurality of first protecting fins immediately adjacent to the active region has a second length along the first direction, and the second length is longer than the first length.

Abstract translation: 半导体集成器件包括具有限定在其上的有源区的衬底，位于有源区中的多个有源鳍，和围绕有源区的多个第一保护鳍。 多个活动翅片中的每一个沿着第一方向延伸并且包括沿着第一方向的第一长度。 多个第一保护翅片沿第一方向延伸。 紧邻有源区域的多个第一保护片之一具有沿第一方向的第二长度，第二长度比第一长度长。