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21.
公开(公告)号:US10991820B2
公开(公告)日:2021-04-27
申请号:US16953286
申请日:2020-11-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chun-Ming Chang , Wen-Jung Liao
IPC: H01L29/778 , H01L29/66 , H01L21/02
Abstract: A method of forming an insulating structure of a high electron mobility transistor (HEMT) is provided, the method including: forming a gallium nitride layer, forming an aluminum gallium nitride layer on the gallium nitride layer, performing an ion doping step to dope a plurality of ions in the gallium nitride layer and the aluminum gallium nitride layer, forming an insulating doped region in the gallium nitride layer and the aluminum gallium nitride layer, forming two grooves on both sides of the insulating doped region, and filling an insulating layer in the two grooves and forming two sidewall insulating structures respectively positioned at two sides of the insulating doped region.
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公开(公告)号:US20210083085A1
公开(公告)日:2021-03-18
申请号:US16659579
申请日:2019-10-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chun-Ming Chang , Wen-Jung Liao
IPC: H01L29/778 , H01L29/20 , H01L29/66 , H01L29/06
Abstract: A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer, a group III-V gate structure and a group III-V patterned structure. The group III-V body layer and the group III-V barrier layer are disposed on the substrate. The group III-V gate structure is disposed on the group III-V barrier layer within the active region. The group III-V patterned structure is disposed on the group III-V barrier layer within the isolation region. The composition of the group III-V patterned structure is the same as the composition of the group III-V gate structure.
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公开(公告)号:US20210036138A1
公开(公告)日:2021-02-04
申请号:US16558329
申请日:2019-09-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chun-Ming Chang , Chun-Liang Hou , Wen-Jung Liao
IPC: H01L29/778 , H01L29/20 , H01L21/306 , H01L29/66
Abstract: A high electron mobility transistor (HEMT) includes a substrate; a buffer layer over the substrate, a GaN layer over the buffer layer, a first AlGaN layer over the GaN layer, a first AlN layer over the AlGaN layer, and a p-GaN layer over the first AlN layer.
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24.
公开(公告)号:US20210013335A1
公开(公告)日:2021-01-14
申请号:US16525525
申请日:2019-07-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chun-Ming Chang , Wen-Jung Liao
IPC: H01L29/778 , H01L29/66 , H01L21/02
Abstract: An insulating structure of a high electron mobility transistor (HEMT) is provided, which comprises a gallium nitride layer, an aluminum gallium nitride layer disposed on the gallium nitride layer, an insulating doped region disposed in the gallium nitride layer and the aluminum gallium nitride layer, and two sidewall insulating structures disposed at two sides of the insulating doped region respectively.
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25.
公开(公告)号:US20210013332A1
公开(公告)日:2021-01-14
申请号:US16519008
申请日:2019-07-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chun-Ming Chang , Wen-Jung Liao
IPC: H01L29/778 , H01L23/31 , H01L29/66 , H01L21/3105
Abstract: An insulating structure of a high electron mobility transistor (HEMT) is provided, which comprises a gallium nitride layer, an aluminum gallium nitride layer disposed on the gallium nitride layer, a groove disposed in the gallium nitride layer and the aluminum gallium nitride layer, an insulating layer disposed in the groove, wherein a top surface of the insulating layer is aligned with a top surface of the aluminum gallium nitride layer, and a passivation layer, disposed on the aluminum gallium nitride layer and the insulating layer.
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公开(公告)号:US10861970B1
公开(公告)日:2020-12-08
申请号:US16596773
申请日:2019-10-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chun-Ming Chang , Chun-Liang Hou , Wen-Jung Liao , Ming-Chang Lu
IPC: H01L29/20 , H01L29/78 , H01L29/66 , H01L29/778
Abstract: A semiconductor epitaxial structure with reduced defects, including a substrate with a recess formed thereon, an island insulator on a bottom surface of the recess, spacers on sidewalls of the recess, a buffer layer in the recess and covering the island insulator, a channel layer in the recess and on the buffer layer, and a barrier layer in the recess and on the channel layer, wherein two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) is formed in the channel layer.
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公开(公告)号:US09171127B1
公开(公告)日:2015-10-27
申请号:US14509074
申请日:2014-10-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chun-Liang Hou , Wen-Jung Liao , Chi-Fang Huang , Yi-Jung Chang
IPC: G06F17/50
CPC classification number: G06F17/5081 , G03F7/70433
Abstract: A design layout generating method is provided. A design layout including a first pattern and a second pattern is provided to a computer system, wherein the first pattern and the second pattern meet a design rule of an integrated circuit, respectively. The first pattern and the second pattern are combined into a third pattern. Next, the third pattern is checked if it meets a definition of a weak pattern, wherein the weak pattern is a pattern that meets the design rule but still forms defects. Then, the third pattern is modified and a new design layout is generated.
Abstract translation: 提供了一种设计布局生成方法。 将包括第一图案和第二图案的设计布局提供给计算机系统,其中第一图案和第二图案分别满足集成电路的设计规则。 第一图案和第二图案被组合成第三图案。 接下来,如果它符合弱图案的定义,则检查第三图案,其中弱图案是符合设计规则但仍形成缺陷的图案。 然后,修改第三个模式并生成新的设计布局。
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公开(公告)号:US12266701B2
公开(公告)日:2025-04-01
申请号:US18199359
申请日:2023-05-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Tung Yeh , Chun-Liang Hou , Wen-Jung Liao , Chun-Ming Chang , Yi-Shan Hsu , Ruey-Chyr Lee
IPC: H01L29/417 , H01L29/06 , H01L29/20 , H01L29/205 , H01L29/40 , H01L29/66 , H01L29/778
Abstract: A high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation layer and the mesa structure. The mesa structure includes a channel layer, a barrier layer on the channel layer, two opposite first edges extending along a first direction, and two opposite second edges extending along a second direction. The contact structure includes a body portion and a plurality of protruding portions. The body portion penetrates through the passivation layer. The protruding portions penetrate through the barrier layer and a portion of the channel layer. In a top view, the body portion overlaps the two opposite first edges of the mesa structure without overlapping the two opposite second edges of the mesa structure.
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公开(公告)号:US12125885B2
公开(公告)日:2024-10-22
申请号:US17401301
申请日:2021-08-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Tung Yeh , Wen-Jung Liao
IPC: H01L29/778 , H01L29/20 , H01L29/66
CPC classification number: H01L29/2003 , H01L29/66431 , H01L29/7786 , H01L29/7787
Abstract: A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, and a p-type doped III-V compound layer. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the III-V compound barrier layer are substantially coplanar.
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公开(公告)号:US20240038871A1
公开(公告)日:2024-02-01
申请号:US17896106
申请日:2022-08-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Tung Yeh , Wen-Jung Liao
IPC: H01L29/66 , H01L29/20 , H01L29/778 , H01L21/02
CPC classification number: H01L29/66462 , H01L29/2003 , H01L29/7786 , H01L21/02458 , H01L21/0254
Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a hole injection buffer layer (HIBL) on the p-type semiconductor layer, and forming a gate electrode on the HIBL.
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