Manufacturing method for forming insulating structure of high electron mobility transistor

    公开(公告)号:US10991820B2

    公开(公告)日:2021-04-27

    申请号:US16953286

    申请日:2020-11-19

    Abstract: A method of forming an insulating structure of a high electron mobility transistor (HEMT) is provided, the method including: forming a gallium nitride layer, forming an aluminum gallium nitride layer on the gallium nitride layer, performing an ion doping step to dope a plurality of ions in the gallium nitride layer and the aluminum gallium nitride layer, forming an insulating doped region in the gallium nitride layer and the aluminum gallium nitride layer, forming two grooves on both sides of the insulating doped region, and filling an insulating layer in the two grooves and forming two sidewall insulating structures respectively positioned at two sides of the insulating doped region.

    SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

    公开(公告)号:US20210083085A1

    公开(公告)日:2021-03-18

    申请号:US16659579

    申请日:2019-10-22

    Abstract: A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer, a group III-V gate structure and a group III-V patterned structure. The group III-V body layer and the group III-V barrier layer are disposed on the substrate. The group III-V gate structure is disposed on the group III-V barrier layer within the active region. The group III-V patterned structure is disposed on the group III-V barrier layer within the isolation region. The composition of the group III-V patterned structure is the same as the composition of the group III-V gate structure.

    Layout generating method
    27.
    发明授权
    Layout generating method 有权
    布局生成方法

    公开(公告)号:US09171127B1

    公开(公告)日:2015-10-27

    申请号:US14509074

    申请日:2014-10-08

    CPC classification number: G06F17/5081 G03F7/70433

    Abstract: A design layout generating method is provided. A design layout including a first pattern and a second pattern is provided to a computer system, wherein the first pattern and the second pattern meet a design rule of an integrated circuit, respectively. The first pattern and the second pattern are combined into a third pattern. Next, the third pattern is checked if it meets a definition of a weak pattern, wherein the weak pattern is a pattern that meets the design rule but still forms defects. Then, the third pattern is modified and a new design layout is generated.

    Abstract translation: 提供了一种设计布局生成方法。 将包括第一图案和第二图案的设计布局提供给计算机系统,其中第一图案和第二图案分别满足集成电路的设计规则。 第一图案和第二图案被组合成第三图案。 接下来,如果它符合弱图案的定义,则检查第三图案,其中弱图案是符合设计规则但仍形成缺陷的图案。 然后,修改第三个模式并生成新的设计布局。

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