公开(公告)号：US20100088544A1

公开(公告)日：2010-04-08

申请号：US12633840

申请日：2009-12-09

Applicant: Norihito GOMYO ,  Ryuichi SUNAYAMA

Inventor： Norihito GOMYO ,  Ryuichi SUNAYAMA

IPC: G06F11/14

CPC classification number: G06F11/1405

Abstract: A processor is provided that is capable of concurrently processing a sequence of instructions for a plurality of threads achieving the retry success rate equivalent to the success rate in processors that process a sequence of instructions for a single thread. An arithmetic device 200 is provided with an instruction execution circuit 201 for executing a plurality of threads, or an execution control circuit 202 for controlling the execution state or rerunning of the threads.

Abstract translation: 提供了一种处理器，其能够同时处理多个线程的指令序列，其实现与处理单个线程的指令序列的处理器中的成功率相当的重试成功率。 算术装置200具有用于执行多个线程的指令执行电路201，或者用于控制线程的执行状态或重新运行的执行控制电路202。

公开(公告)号：US07653834B2

公开(公告)日：2010-01-26

申请号：US11384236

申请日：2006-03-17

Applicant: William Henry Mangione-Smith

Inventor： William Henry Mangione-Smith

IPC: G06F11/00

CPC classification number: G06F11/1407 ,  G06F1/263 ,  G06F1/3203 ,  G06F1/3296 ,  G06F11/0706 ,  G06F11/0793 ,  G06F11/1405 ,  G06F11/3471 ,  Y02D10/172

Abstract: Embodiments include a system, an apparatus, a device, and a method. An apparatus includes a synchronous circuit including a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane voltage. The apparatus also includes an error detector operable to detect an incidence of a computational error occurring in the first subcircuit. The apparatus includes a controller operable to change the first power plane voltage based upon the detected incidence of a computational error. The apparatus also includes a power supply configured to electrically couple with a portable power source and operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

Abstract translation: 实施例包括系统，装置，装置和方法。 一种装置包括同步电路，其包括由具有第一电力平面电压的第一电力平面供电的第一子电路和由具有第二电力平面电压的第二电力平面供电的第二子电路。 该装置还包括可操作以检测在第一子电路中发生的计算错误的入射的误差检测器。 该装置包括可操作以基于检测到的计算误差的入射来改变第一功率面电压的控制器。 该装置还包括被配置为与便携式电源电耦合并且可操作以响应于控制器向第一电源平面提供至少两个电压中的选定的一个的电源。

公开(公告)号：US20090183035A1

公开(公告)日：2009-07-16

申请号：US11972166

申请日：2008-01-10

Applicant: Michael G. Butler ,  Nhon Quach

Inventor： Michael G. Butler ,  Nhon Quach

IPC: G06F9/302 ,  G06F11/14

CPC classification number: G06F11/1497 ,  G06F11/1405 ,  G06F11/1641 ,  G06F11/1645

Abstract: A processor core includes an instruction decode unit that may dispatch a same integer instruction stream to a plurality of integer execution units and may consecutively dispatch a same floating-point instruction stream to a floating-point unit. The integer execution units may operate in lock-step such that during each clock cycle, each respective integer execution unit executes the same integer instruction. The floating-point unit may execute the same floating-point instruction stream twice. Prior to the integer instructions retiring, compare logic may detect a mismatch between execution results from each of the integer execution units. In addition, prior to the results of the floating-point instruction stream transferring out of the floating-point unit, the compare logic may also detect a mismatch between results of execution of each consecutive floating-point instruction stream. Further, in response to detecting any mismatch, the compare logic may cause instructions causing the mismatch to be re-executed.

Abstract translation: 处理器核心包括指令解码单元，其可以向多个整数执行单元分派相同的整数指令流，并且可以将相同的浮点指令流连续地分派到浮点单元。 整数执行单元可以锁定步骤操作，使得在每个时钟周期期间，每个相应的整数执行单元执行相同的整数指令。 浮点单元可以执行相同的浮点指令流两次。 在整数指令退出之前，比较逻辑可以检测来自每个整数执行单元的执行结果之间的不匹配。 此外，在浮点指令流从浮点单元传出的结果之前，比较逻辑还可以检测每个连续浮点指令流的执行结果之间的不匹配。 此外，响应于检测到任何不匹配，比较逻辑可能导致导致不匹配的指令被重新执行。

公开(公告)号：US07516366B2

公开(公告)日：2009-04-07

申请号：US11840439

申请日：2007-08-17

Applicant: Yosef Lev ,  Jan-Willem Maessen

Inventor： Yosef Lev ,  Jan-Willem Maessen

IPC: G06F11/00

CPC classification number: G06F9/466 ,  G06F11/1405

Abstract: Split hardware transaction techniques may support execution of serial and parallel nesting of code within an atomic block to an arbitrary nesting depth. An atomic block including child code sequences nested within a parent code sequence may be executed using separate hardware transactions for each child, but the execution of the parent code sequence, the child code sequences, and other code within the atomic block may appear to have been executed as a single transaction. If a child transaction fails, it may be retried without retrying the parent code sequence or other child code sequences. Before a child transaction is executed, a determination of memory consistency may be made. If a memory inconsistency is detected, the child transaction may be retried or control may be returned to its parent. Memory inconsistencies between parallel child transactions may be resolved by serializing their execution before retrying at least one of them.

Abstract translation: 分割硬件事务技术可以支持将原子块内的代码的串行和并行嵌套执行到任意的嵌套深度。 包含嵌套在父代码序列中的子代码序列的原子块可以使用针对每个子代的单独的硬件事务执行，但是原子块中的父代码序列，子代码序列和其他代码的执行可能看起来已经被 作为单个事务执行。 如果子事务失败，则可以重试该子事务而不重试父代码序列或其他子代码序列。 在执行子事务之前，可以确定内存一致性。 如果检测到内存不一致，则可能会重试子进程，或者可以将控制权返回给其父进程。 并行子事务之间的内存不一致可以通过在重新执行其中的至少一个之前对其执行进行序列化来解决。

公开(公告)号：US07512842B2

公开(公告)日：2009-03-31

申请号：US11384237

申请日：2006-03-17

Applicant: William Henry Mangione-Smith

Inventor： William Henry Mangione-Smith

IPC: G06F11/00

CPC classification number: G06F11/1407 ,  G06F1/263 ,  G06F1/3203 ,  G06F1/3296 ,  G06F11/0706 ,  G06F11/0793 ,  G06F11/1405 ,  G06F11/3471 ,  Y02D10/172

Abstract: Embodiments include a system, a device, and a method. A computing system includes a synchronous circuit. The synchronous circuit includes a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane voltage. The system also includes an error detector operable to detect an incidence of a computational error occurring in the first subcircuit. The system further includes a controller operable to change the first power plane voltage based upon the detected incidence of a computational error. The system may include a power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

Abstract translation: 实施例包括系统，设备和方法。 计算系统包括同步电路。 同步电路包括由具有第一电力平面电压的第一电力平面供电的第一子电路和由具有第二电力平面电压的第二电力平面供电的第二子电路。 该系统还包括可操作以检测在第一子电路中发生的计算误差的入射的误差检测器。 该系统还包括控制器，其可操作以基于检测到的计算误差的入射来改变第一功率面电压。 该系统可以包括可操作以响应于控制器向至少两个电压提供选定的一个电压的电源。

公开(公告)号：US20090057565A1

公开(公告)日：2009-03-05

申请号：US11936636

申请日：2007-11-07

Applicant: Eric C. Hannah

Inventor： Eric C. Hannah

IPC: G01T1/24 ,  G01T1/178

CPC classification number: G06F11/1405 ,  H01L23/556 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A cosmic ray detector includes a cantilever with a first tip. The detector also includes a second tip and circuitry to provide a signal indicative of a distance between the first and second tips being such as would be caused by a cosmic ray interaction event.

Abstract translation: 宇宙射线检测器包括具有第一尖端的悬臂。 检测器还包括第二尖端和提供指示第一和第二尖端之间的距离的信号的电路，其将由宇宙射线相互作用事件引起。

公开(公告)号：US20070050582A1

公开(公告)日：2007-03-01

申请号：US11384237

申请日：2006-03-17

Applicant: William Henry Mangione-Smith

Inventor： William Henry Mangione-Smith

IPC: G06F12/00

CPC classification number: G06F11/1407 ,  G06F1/263 ,  G06F1/3203 ,  G06F1/3296 ,  G06F11/0706 ,  G06F11/0793 ,  G06F11/1405 ,  G06F11/3471 ,  Y02D10/172

Abstract: Embodiments include a system, a device, and a method. A computing system includes a synchronous circuit. The synchronous circuit includes a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane voltage. The system also includes an error detector operable to detect an incidence of a computational error occurring in the first subcircuit. The system further includes a controller operable to change the first power plane voltage based upon the detected incidence of a computational error. The system may include a power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

Abstract translation: 实施例包括系统，设备和方法。 计算系统包括同步电路。 同步电路包括由具有第一电力平面电压的第一电力平面供电的第一子电路和由具有第二电力平面电压的第二电力平面供电的第二子电路。 该系统还包括可操作以检测在第一子电路中发生的计算误差的入射的误差检测器。 该系统还包括控制器，其可操作以基于检测到的计算误差的入射来改变第一功率面电压。 该系统可以包括可操作以响应于控制器向至少两个电压提供选定的一个电压的电源。

公开(公告)号：US20070050581A1

公开(公告)日：2007-03-01

申请号：US11384236

申请日：2006-03-17

Applicant: William Mangione-Smith

Inventor： William Mangione-Smith

IPC: G06F12/00

CPC classification number: G06F11/1407 ,  G06F1/263 ,  G06F1/3203 ,  G06F1/3296 ,  G06F11/0706 ,  G06F11/0793 ,  G06F11/1405 ,  G06F11/3471 ,  Y02D10/172

Abstract: Embodiments include a system, an apparatus, a device, and a method. An apparatus includes a synchronous circuit including a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane voltage. The apparatus also includes an error detector operable to detect an incidence of a computational error occurring in the first subcircuit. The apparatus includes a controller operable to change the first power plane voltage based upon the detected incidence of a computational error. The apparatus also includes a power supply configured to electrically couple with a portable power source and operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

Abstract translation: 实施例包括系统，装置，装置和方法。 一种装置包括同步电路，其包括由具有第一电力平面电压的第一电力平面供电的第一子电路和由具有第二电力平面电压的第二电力平面供电的第二子电路。 该装置还包括可操作以检测在第一子电路中发生的计算错误的入射的误差检测器。 该装置包括可操作以基于检测到的计算误差的入射来改变第一功率面电压的控制器。 该装置还包括被配置为与便携式电源电耦合并且可操作以响应于控制器向第一电源平面提供至少两个电压中的选定的一个的电源。

公开(公告)号：US20030177309A1

公开(公告)日：2003-09-18

申请号：US10175099

申请日：2002-06-20

Inventor： Dong Jae Kang ,  Bum Joo Shin ,  Chang Soo Kim ,  Young Ho Kim ,  Yu Hyeon Bak

IPC: G06F012/16 ,  G06F012/00

CPC classification number: G06F11/2064 ,  G06F11/1405 ,  G06F11/2087

Abstract: Disclosed is a coherence preservation method of duplicated data in RAID subsystem. The method comprises the steps of: if a read operation is requested by the RAID subsystem, selecting an arbitrary target disk among disks having duplicated data, and implementing the read operation on the selected disk; implementing a read error handling to determine whether an error occurs in the disks selected upon the read operation, and if the error occurs in the read operation of the selected target disk, repeating the read error handling until the read operation of the data succeeds by circulating the remaining metering-treated disks in turns; after the read error handling, if the read operation on the remaining disk in all succeeds, completing the read error handling, and if the read operation on the remaining disk in all fails, returning the error to the disk, and completing the read error handling; if a write operation is requested by the RAID subsystem, implementing the write operation on the disks having duplicated data; after implementing the write operation, if a temporary error occurs in the duplicated data, implementing a temporary error handling to maintain the data coherence in the disks having the duplicated data and to recover the temporary error; and after implementing the write operation, if a permanent error occurs in the duplicated data, implementing a permanent error handling to maintain the data coherence in the disks having the duplicated data and to recover the permanent error.

Abstract translation: 披露了RAID子系统中重复数据的一致性保存方法。 该方法包括以下步骤：如果RAID子系统要求读取操作，则在具有复制数据的盘中选择任意的目标盘，并在所选择的盘上实现读取操作; 执行读取错误处理以确定在读取操作中选择的磁盘中是否发生错误，并且如果在所选择的目标盘的读取操作中发生错误，则重复读取错误处理，直到数据的读取操作成功通过循环 剩余的计量处理盘轮流; 在读取错误处理之后，如果剩余磁盘上的读取操作全部成功，完成读取错误处理，并且如果所有剩余磁盘上的读取操作全部失败，则将错误返回到磁盘，并完成读取错误处理 ; 如果RAID子系统要求写操作，则在具有重复数据的磁盘上实现写操作; 在执行写入操作之后，如果在复制数据中发生临时错误，则执行临时错误处理以维持具有复制数据的磁盘中的数据一致性并恢复临时错误; 并且在实施写操作之后，如果在复制数据中发生永久性错误，则实施永久性错误处理以维持具有复制数据的盘中的数据一致性并恢复永久错误。

公开(公告)号：US06543028B1

公开(公告)日：2003-04-01

申请号：US09540295

申请日：2000-03-31

Applicant: Sujat Jamil ,  Hang T. Nguyen ,  Andres Rabago

Inventor： Sujat Jamil ,  Hang T. Nguyen ,  Andres Rabago

IPC: H03M1300

CPC classification number: G06F11/1032 ,  G06F11/1405 ,  H03M13/11

Abstract: A technique to detect and correct corruption of instructions by soft errors. A parity bit is propagated with an instruction through the instruction flow path and checked at selected places. When a parity error is detected, a replay circuit is used to perform a replay to reload the instruction to remove the corrupted instruction.

Abstract translation: 一种通过软错误检测和纠正指令损坏的技术。 奇偶校验位通过指令流程路径传播并在选定的地方进行检查。 当检测到奇偶校验错误时，使用重播电路执行重播以重新加载指令以去除损坏的指令。