公开(公告)号：US09753828B1

公开(公告)日：2017-09-05

申请号：US14831138

申请日：2015-08-20

Applicant: EMC IP Holding Company LLC

Inventor： Preston F. Crow ,  Preethi Natarajan ,  Steven T. McClure

IPC: G06F11/30 ,  G06F1/30 ,  G06F3/06 ,  G06F12/08 ,  G06F12/0868

CPC classification number: G06F11/3058 ,  G06F1/30 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/068 ,  G06F11/1441 ,  G06F11/2015 ,  G06F11/2071 ,  G06F11/30 ,  G06F11/3034 ,  G06F11/3037 ,  G06F11/3055 ,  G06F12/0868 ,  G06F2201/81 ,  G06F2212/1032 ,  G06F2212/21 ,  G06F2212/281 ,  G06F2212/313

Abstract: Maintaining failure survivability in a storage system includes determining a save time corresponding to an amount of time needed to transfer system data from volatile memory to non-volatile memory, determining a threshold corresponding to time for batteries to run while transferring data from volatile memory to non-volatile memory after a power loss, and providing an indication in response to the save time being greater than the threshold. The system may include a plurality of directors and the save time and the threshold may be determined for each of the directors. Determining a threshold may include determining an amount of battery time provided by battery power following power loss and multiplying the amount of battery time by a factor less than one, such as 0.8.

公开(公告)号：US09750164B2

公开(公告)日：2017-08-29

申请号：US15291005

申请日：2016-10-11

Applicant: Switch, Ltd.

Inventor： Rob Roy

IPC: H05K7/20

CPC classification number: H05K13/00 ,  F25B25/005 ,  F25B2700/173 ,  G06F1/20 ,  G06F11/2015 ,  G06F11/3062 ,  G06F2200/201 ,  H05K5/0213 ,  H05K7/20145 ,  H05K7/20709 ,  H05K7/20745

Abstract: Described herein is an integrated data center that provides for efficient cooling, as well as efficient wire routing.

公开(公告)号：US09710343B2

公开(公告)日：2017-07-18

申请号：US14670758

申请日：2015-03-27

Applicant: Facebook, Inc.

Inventor： Christian Markus Petersen

IPC: G06F11/00 ,  G06F11/20 ,  G06F1/30 ,  G06F11/30

CPC classification number: G06F11/2015 ,  G06F1/30 ,  G06F11/3034 ,  G06F11/3058

Abstract: Some embodiments include a multi-storage-device array (e.g., a SSD tray, a SSD sled or a SSD rack) having multiple drives (e.g., solid-state drives). The multi-storage-device array can have an enclosure around the drives, a processor and a network interface, and implement a power failure management circuit. The power failure management circuit can include an electric probe that detects a power failure. Upon detecting the power failure, the power failure management circuit sends an interrupt signal to a drive controller to flush data in volatile-memory (e.g., write cache, firmware cache, look-up table cache, or other random access memory) into non-volatile memory (e.g., flash memory). The power failure management circuit can include a system-level holdup energy storage that retains power after power failure to support flushing of the data from the volatile memory during the power failure.

公开(公告)号：US09703650B1

公开(公告)日：2017-07-11

申请号：US14991954

申请日：2016-01-10

Applicant: Cisco Technology, Inc.

Inventor： Charles Calvin Byers ,  Gonzalo Salgueiro ,  Joseph M. Clarke

IPC: G06F11/00 ,  G06F11/20 ,  G06F1/30

CPC classification number: G06F11/2015 ,  G06F1/263 ,  G06F1/30 ,  G06F2201/805

Abstract: In one embodiment, a data processing device includes power port units for connection to network devices. Each power port unit is selectively configurable to operate as either (i) a Power Source Equipment port unit to provide power to a network device, or (ii) a Powered Device (PD) port unit to sink power from a network device. The device also includes a processor. In response to a power supply failure, the processor is operative to poll at least two network devices to determine if they are able to supply power, receive a response from each of the at least two network devices, and configure at least two power port units as PD port units to sink power from the at least two network devices. At least part of the received power is transferred from the at least two power port units via a power summing node to at least one local load.

公开(公告)号：US20170132097A1

公开(公告)日：2017-05-11

申请号：US14934699

申请日：2015-11-06

Applicant: Chicony Power Technology Co., Ltd.

Inventor： Chun-Hsiung WANG ,  Kai-Ming CHEN ,  Shing-Feng YANG

IPC: G06F11/20 ,  G06F1/30

CPC classification number: G06F11/2015 ,  G06F1/30 ,  G06F2201/805 ,  G06F2201/81

Abstract: A power supply apparatus with reverse current protection includes a digital signal processor, a secondary side rectifying circuit, a voltage detection unit and a current detection unit. A plurality of the power supply apparatuses are connected in parallel and applied to a server system. When the voltage detection unit detects that a bus voltage is greater than a predetermined voltage and the current detection unit detects that an output current is less than a predetermined current, the voltage detection unit and the current detection unit inform the digital signal processor that the bus voltage is greater than the predetermined voltage and the output current is less than the predetermined current respectively, so that the digital signal processor turns off the secondary side rectifying circuit to stop outputting power.

公开(公告)号：US09614365B2

公开(公告)日：2017-04-04

申请号：US14220905

申请日：2014-03-20

Applicant: Cisco Technology, Inc.

Inventor： Weizhong Tang ,  Sung Kee Baek ,  Craig Zimmerman

IPC: H02H7/12 ,  G06F1/26 ,  H04M19/08 ,  G06F11/16

CPC classification number: H02H7/1213 ,  G06F1/26 ,  G06F11/16 ,  G06F11/2015 ,  H03K17/0822 ,  H04M19/08

Abstract: A system and method for preventing bus voltage sagging when an Oring-FET in an N+1 redundant power supply configuration is faulty during power up. Each redundant power supply includes an Oring-FET and a voltage comparator. The voltage comparator receives and compares an input voltage and an output voltage of the Oring-FET during power up. In the event input voltage is less than the output voltage, the Oring-FET is deemed to be operating properly and provides output to a communicatively coupled system bus in response to the input voltage reaching a predetermined voltage threshold level. In the event the input voltage is approximately equal to the output voltage, the voltage comparator assists in preventing inrush current from flowing from the communicatively coupled system bus and prevents voltage sagging on the communicatively coupled system bus when another redundant power supply configuration is providing power to the communicatively coupled system bus.

公开(公告)号：US20170091054A1

公开(公告)日：2017-03-30

申请号：US15345116

申请日：2016-11-07

Applicant: NetApp, Inc.

Inventor： William Patrick Delaney ,  Joseph Russell Blount ,  Rodney A. DeKoning

IPC: G06F11/20 ,  G06F11/14 ,  G06F12/0808 ,  G06F12/128 ,  G06F11/10 ,  G06F3/06

CPC classification number: G06F11/2015 ,  G06F3/0607 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G06F3/0689 ,  G06F11/1064 ,  G06F11/1092 ,  G06F11/1441 ,  G06F11/1451 ,  G06F12/0808 ,  G06F12/12 ,  G06F12/128 ,  G06F2211/1009 ,  G06F2211/1028 ,  G06F2212/621

Abstract: Methods and systems for storing data at a storage device of a storage system are provided. The data is first temporarily stored at a first write cache and an input/output request for a persistence storage device used as a second write cache is generated, when an I/O request size including the received data has reached a threshold value. The data from the first cache is transferred to the persistence storage device and a recovery control block with a location of the data stored at the persistence storage device is updated. An entry is added to a linked list that is used to track valid data stored at the persistence storage device and then the data is transferred from the persistence storage device to the storage device of the storage system.

公开(公告)号：US09594517B2

公开(公告)日：2017-03-14

申请号：US14761273

申请日：2013-12-12

Applicant: DENSO CORPORATION

Inventor： Takaomi Hasegawa

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06 ,  G06F11/14 ,  G06F11/20

CPC classification number: G06F3/0617 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0683 ,  G06F11/1441 ,  G06F11/2015

Abstract: A vehicle device is provided that includes a first processer for processing first data classified as a first category when being supplied based on a vehicle-mounted power source, a second processor for processing second data classified as a second category when being supplied based on the vehicle-mounted power source, an external data storage externally attached to both the first and second processors, and a built-in data storage provided in the second processor and capable of retaining the stored second data even if a battery voltage decreases to a predetermined value for a predetermined period of time. At least one of the first and second processors varies a storage destination and a storage frequency in accordance with priorities. The second processor constantly stores at least part of the second data in the built-in data storage.

Abstract translation: 提供了一种车辆装置，其包括：第一处理器，用于处理当基于车载电源供应时被分类为第一类别的第一数据;第二处理器，用于处理当基于车辆提供时被分类为第二类别的第二数据 外部数据存储器外部附接到第一和第二处理器，以及内置的数据存储器，其设置在第二处理器中，并且能够保持所存储的第二数据，即使电池电压降低到预定值， 一段预定的时间。 第一和第二处理器中的至少一个根据优先级改变存储目的地和存储频率。 第二处理器将至少部分第二数据存储在内置数据存储器中。

公开(公告)号：US20170060436A1

公开(公告)日：2017-03-02

申请号：US14843581

申请日：2015-09-02

Applicant: Intel Corporation

Inventor： Sanjeev N. Trika ,  Knut S. Grimsrud ,  Piotr Wysocki

IPC: G06F3/06 ,  G06F11/20

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/068 ,  G06F11/2015 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0888 ,  G06F2201/805 ,  G06F2212/7203 ,  Y02D10/13

Abstract: Technologies for establishing and managing a high-performance memory region of a solid state drive include reserving a region of a volatile memory of the solid state drive for storage of host data. Memory accesses received from a host may be directed toward the reserved region of the volatile memory or toward a non-volatile memory of the solid state drive. Due to the structure of the volatile memory, memory accesses to the reserved region may exhibit lower access timing relative to memory accesses to the non-volatile memory. As such, the reserved region may be utilized as storage space for journaling and logging of data and/or other applications. Upon shutdown or a power failure event, data stored in the reserved region of the volatile memory is copied to the non-volatile memory and subsequently reinstated to the volatile memory upon the next initialization event.

Abstract translation: 用于建立和管理固态驱动器的高性能存储器区域的技术包括保留用于存储主机数据的固态驱动器的易失性存储器的区域。 从主机接收到的存储器访问可以指向易失性存储器的保留区域或朝向固态驱动器的非易失性存储器。 由于易失性存储器的结构，相对于对非易失性存储器的存储器访问，对保留区域的存储器访问可以呈现较低的访问时序。 因此，保留区域可以用作用于日志记录和记录数据和/或其他应用的存储空间。 在关闭或电源故障事件时，存储在易失性存储器的保留区域中的数据被复制到非易失性存储器中，并且随后在下一个初始化事件时恢复到易失性存储器。

公开(公告)号：US09575850B2

公开(公告)日：2017-02-21

申请号：US14788867

申请日：2015-07-01

Applicant: BULL SAS

Inventor： Georges Lecourtier

IPC: G06F11/00 ,  G06F11/14 ,  G06F9/48 ,  G06F11/16 ,  G06F11/20

CPC classification number: G06F11/1474 ,  G06F9/4887 ,  G06F11/1484 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/2015 ,  G06F11/2028 ,  G06F11/2038 ,  G06F11/2046 ,  G06F11/2097 ,  G06F2201/87

Abstract: A method for synchronously running an application in a high availability environment including a plurality of calculating modules interconnected by a very high-speed broad band network, includes: configuring the modules into partitions including a primary and a secondary partition and a monitoring partition; running the application on each running partition, inputs-outputs processed by the primary partition transmitted to the secondary running partition via the monitoring partition; synchronizing the runnings via exploiting microprocessor context changes; transmitting a catastrophic error signal to the monitoring partition; continuing the running by switching to a degraded mode, the running continuing on a single partition.

Abstract translation: 一种用于在高可用性环境中同步运行应用的方法，包括由非常高速的宽带网络互连的多个计算模块，包括：将模块配置成包括主分区和辅分区和监控分区的分区; 在每个运行分区上运行应用程序，由主分区处理的输入输出通过监控分区发送到辅助运行分区; 通过利用微处理器上下文更改来同步运行; 向监控分区发送灾难性错误信号; 通过切换到降级模式继续运行，运行在单个分区上继续运行。