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    STORAGE CLUSTER
    21.
    发明申请
    STORAGE CLUSTER 有权
    存储群集

    公开(公告)号：US20150355848A1

    公开(公告)日：2015-12-10

    申请号：US14610766

    申请日：2015-01-30

    Applicant: Pure Storage, Inc.

    Inventor： John Hayes ,  John Colgrove ,  John D. Davis

    IPC: G06F3/06

    CPC classification number: G06F11/1076 ,  G06F3/06 ,  G06F3/0607 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/067 ,  G06F3/0688 ,  G06F11/1068 ,  G06F11/108 ,  G06F11/1092 ,  G06F12/0246 ,  G06F2201/845 ,  G06F2212/7206 ,  G06F2212/7207 ,  H03M13/154

    Abstract: A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. A plurality of compute nodes is included in the single chassis, each of the plurality of compute nodes is configured to communicate with the plurality of storage nodes. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.

    Abstract translation: 提供了单个机箱中的多个存储节点。 单个机箱中的多个存储节点被配置为一起作为存储集群通信。 多个存储节点中的每一个包括用于用户数据存储的非易失性固态存储器。 多个存储节点被配置为在整个多个存储节点中分配与用户数据相关联的用户数据和元数据，使得多个存储节点使用擦除编码保持读取用户数据的能力，尽管丢失了两个 的多个存储节点。 多个计算节点包括在单个机箱中，多个计算节点中的每一个被配置为与多个存储节点进行通信。 还提供了一种用于访问具有非易失性固态存储器的多个存储节点中的用户数据的方法。

    Symmetric Multi-Processor Arrangement, Safety Critical System, And Method Therefor
    22.
    发明申请
    Symmetric Multi-Processor Arrangement, Safety Critical System, And Method Therefor 审中-公开
    对称多处理器布置，安全关键系统及其方法

    公开(公告)号：US20150254123A1

    公开(公告)日：2015-09-10

    申请号：US14432938

    申请日：2012-10-01

    Applicant: ABB Technology Ltd

    Inventor： Trond Loekstad ,  Frank Reichenbach

    IPC: G06F11/07 ,  G06F9/455

    CPC classification number: G06F11/079 ,  G06F9/45558 ,  G06F11/0721 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/18 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2201/845

    Abstract: A symmetric multi-core processor arrangement for a safety critical system, including: a symmetric multi-processor having at least two cores and a memory shared for the at least two cores; and a hypervisor connected to the symmetric multi-processor, and configured to organize access to the at least two cores for at least a diagnostic application checking the safety critical system; wherein, during use, the diagnostic application is configured to read from and write to the memory, and the hypervisor is configured to read only from the memory.

    Abstract translation: 一种用于安全关键系统的对称多核处理器装置，包括：具有至少两个核的对称多处理器和至少两个核共享的存储器; 以及管理程序，其连接到所述对称多处理器，并且被配置为组织对所述至少两个核的访问以用于检查所述安全关键系统的至少一个诊断应用; 其中，在使用期间，诊断应用被配置为从存储器读取和写入，并且管理程序被配置为仅从存储器读取。

    Package On Package Memory Interface and Configuration With Error Code Correction
    23.
    发明申请
    Package On Package Memory Interface and Configuration With Error Code Correction 审中-公开
    包装封装内存接口和配置与错误代码校正

    公开(公告)号：US20150227421A1

    公开(公告)日：2015-08-13

    申请号：US14587878

    申请日：2014-12-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Rahul Gulati ,  Aishwarya Dubey ,  Nainala Vyagrheswarudu ,  Vasant Easwaran ,  Prashant Dinkar Karandikar ,  Mihir Moody

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/10 ,  G06F2201/845

    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

    Abstract translation: 信息通信电路，包括用于在封装配置上耦合到封装中的第二集成电路的第一集成电路。 第一集成电路包括用于传送信息位的处理电路，并且信息位包括数据位和纠错位，其中纠错位用于指示数据位是否被正确接收。 第二集成电路包括用于接收和存储至少一些信息位的存储器。 信息通信电路还包括接口电路，用于沿着多个导体选择性地在封装配置上的封装之间通信。 在第一种情况下，接口电路仅选择性地仅沿导体数传送数据位。 在第二种情况下，接口电路沿着导体数量的第二组和第二组导体选择性地传送沿导体数量和误差校正位的第一组的数据位。

    STORAGE SYSTEM AND METHOD OF CONTROLLING STORAGE SYSTEM
    24.
    发明申请
    STORAGE SYSTEM AND METHOD OF CONTROLLING STORAGE SYSTEM 有权
    存储系统和控制存储系统的方法

    公开(公告)号：US20150212900A1

    公开(公告)日：2015-07-30

    申请号：US14425675

    申请日：2012-12-05

    Applicant: HITACHI, LTD.

    Inventor： Mitsuo Hayasaka ,  Koji Yamasaki

    IPC: G06F11/14 ,  H04L29/08 ,  G06F17/30

    CPC classification number: G06F11/1453 ,  G06F11/1456 ,  G06F11/1464 ,  G06F11/1469 ,  G06F17/3015 ,  G06F2201/845 ,  H04L67/1097

    Abstract: In a storage system for backing up data of an external apparatus, the external apparatus and a storage apparatus collaboratively perform efficient de-duplication. A storage system stores data from the external apparatus in a unit of content, and includes a backup apparatus configured to execute backup processing to create backup data of the data from the external apparatus in the unit of content; and a storage apparatus coupled to the backup apparatus in a communication-enabled manner and configured to store the backup data received from the backup apparatus. A first backup processing part of the backup apparatus determines whether or not a content is already stored in the storage apparatus by using first redundancy determination information that is information for determining whether or not each of contents of the backup data is already stored in the storage apparatus.

    Abstract translation: 在用于备份外部设备的数据的存储系统中，外部设备和存储设备协同地执行有效的重复数据删除。 存储系统以内容为单位存储来自外部设备的数据，并且包括备份设备，被配置为执行备份处理，以内容为单位从外部设备创建数据的备份数据; 以及存储装置，其以通信方式耦合到所述备份装置，并且被配置为存储从所述备份装置接收的备份数据。 备份装置的第一备份处理部分通过使用作为用于确定备份数据的每个内容是否已经存储在存储装置中的信息的第一冗余确定信息来确定内容是否已经存储在存储装置中 。

    Redundant control device and network system
    26.
    发明授权
    Redundant control device and network system 有权
    冗余控制设备和网络系统

    公开(公告)号：US09030929B2

    公开(公告)日：2015-05-12

    申请号：US13662007

    申请日：2012-10-26

    Applicant: ALAXALA Networks Corporation

    Inventor： Shohei Fukuzaki ,  Ken Watanabe

    IPC: H04L1/22 ,  G06F11/20

    CPC classification number: H04L1/22 ,  G06F11/2007 ,  G06F2201/845

    Abstract: Network repeaters which each implement a redundant switching function previously grasp connection states of ports of a network system by using an inquiry frame and an exchange frame. At the time when a line is broken, when actively confirming a state of a port connected to a port in which a line is broken via a downstream device, the network repeaters each grasp that which portion of the line is broken and determine whether a switchover is required. Through the process, the network repeaters each prevent a useless switchover such as switching-back immediately after the switchover, and at the same time since a mechanism of waiting for a given length of times is not required, they each perform a fast switchover.

    Abstract translation: 每个实现冗余切换功能的网络中继器先前通过使用查询帧和交换帧来掌握网络系统的端口的连接状态。 当线路断开时，当通过下游设备主动确认连接到其中线路断开的端口的端口的状态时，网络中继器各自掌握线路的哪个部分被破坏并且确定是否切换 是必须的。 通过该过程，网络中继器在切换后立即避免无切换的切换，如切换回切，同时由于不需要等待一段时间的机制，因此它们各自进行快速切换。

    INFORMATION PROCESSING SYSTEM AND CONTROL METHOD THEREOF
    28.
    发明申请
    INFORMATION PROCESSING SYSTEM AND CONTROL METHOD THEREOF 有权
    信息处理系统及其控制方法

    公开(公告)号：US20140331084A1

    公开(公告)日：2014-11-06

    申请号：US14358616

    申请日：2012-03-16

    Applicant: Junya Sawazaki ,  Naoki Ikawa ,  Kei Takeda

    Inventor： Junya Sawazaki ,  Naoki Ikawa ,  Kei Takeda

    IPC: G06F3/06 ,  G06F11/14 ,  G06F11/20

    CPC classification number: G06F3/061 ,  G06F3/0631 ,  G06F3/0689 ,  G06F11/1402 ,  G06F11/2058 ,  G06F17/30911 ,  G06F2201/80 ,  G06F2201/845

    Abstract: Information processing system for rapidly performing analysis of semistructured data while preserving fault-tolerance of data for a store request acquiring the number which has been stored of the same and data structures set beforehand, refer to data structure management information to determine a data store unit, instructs replica creation of the data with regard to the data stored in the data store unit in which any of the replicas have been stored, transmits an instruction, for performing a data operation, to a data structure operation unit, whereupon a processing unit, in accordance with the content of an analysis request, performs analysis processing by way of either data stored in any of the data storage units after a data structure operation or data which have not been subject to a data structure operation.

    Abstract translation: 用于快速执行半结构化数据分析的信息处理系统，同时保存用于获取已经存储的数据的存储请求的数据的容错，以及预先设置的数据结构，参考数据结构管理信息来确定数据存储单元， 指示关于存储在其中存储任何副本的数据存储单元中的数据的数据的副本创建，用于执行数据操作的指令发送到数据结构操作单元，在该数据结构操作单元中，处理单元 根据分析请求的内容，通过在数据结构操作之后存储在任何数据存储单元中的数据或者未经过数据结构操作的数据执行分析处理。

    Fault tolerant stability critical execution checking using redundant execution pipelines
    30.
    发明授权
    Fault tolerant stability critical execution checking using redundant execution pipelines 失效
    使用冗余执行管道的容错稳定性关键执行检查

    公开(公告)号：US08707094B2

    公开(公告)日：2014-04-22

    申请号：US13793267

    申请日：2013-03-11

    Applicant: International Business Machines Corporation

    Inventor： Mark J. Hickey ,  Adam J. Muff ,  Matthew R. Tubbs ,  Charles D. Wait

    IPC: G06F11/16 ,  G06F11/00

    CPC classification number: G06F11/0751 ,  G06F9/30185 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3867 ,  G06F11/1641 ,  G06F2201/845

    Abstract: A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the results of the multiple instances of the instructions can be compared for the purpose of detecting errors. For other types of instructions for which fault tolerant or stability critical execution is not required or desired, the redundant execution pipelines are utilized in a more conventional manner, enabling multiple non-stability critical instructions to be concurrently issued to and executed by the redundant execution pipelines. As such, for non-stability critical program code, the performance benefits of having multiple redundant execution units are preserved, yet in the instances where fault tolerant or stability critical execution is desired for certain program code, the redundant execution units may be repurposed to provide greater assurances as to the fault-free execution of such instructions.

    Abstract translation: 电路布置和方法利用处理单元中的现有冗余执行流水线并行执行稳定性关键指令的多个实例，从而可以比较指令的多个实例的结果以便检测错误。 对于不需要或不需要容错或稳定性关键执行的其他类型的指令，以更传统的方式利用冗余执行流水线，使多个非稳定性关键指令同时发布到冗余执行管线并由其执行 。 因此，对于非稳定性关键程序代码，保留具有多个冗余执行单元的性能优点，但是在需要对某些程序代码进行容错或稳定性关键执行的情况下，冗余执行单元可以重新利用以提供 对这种指令的无故障执行的更大保证。

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